Display device and electronic device
First Claim
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1. A display device comprising:
- a driver circuit comprising a plurality of pulse output circuits, each of the plurality of pulse output circuits comprising a first transistor; and
a pixel circuit comprising a second transistor and a third transistor,wherein each of the plurality of pulse output circuits is configured to drive a gate line,wherein the pixel circuit is electrically connected to the gate line,wherein a second layer comprising the second transistor is stacked over a first layer comprising the first transistor and the third transistor,wherein the first transistor and the second transistor overlap with each other,wherein the second transistor is electrically connected to the first transistor through a conductive layer provided in an opening of an insulating layer,wherein the insulating layer is sandwiched between the first transistor and the second transistor,wherein a gate electrode of the second transistor and a gate electrode of the third transistor are directly connected to the gate line, andwherein one of a source and a drain of the third transistor in the first layer is electrically connected to the second transistor in the second layer.
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Abstract
A display device that can be easily and more flexibly designed is provided. The display device includes a pixel circuit and a driver circuit in a display portion. The driver circuit includes a plurality of pulse output circuits. Each of the plurality of pulse output circuits has a function of driving a gate line. The pixel circuit is electrically connected to the gate line. Each of the plurality of pulse output circuits includes a first transistor. The pixel circuit includes a second transistor. A layer including the second transistor is over a layer including the first transistor, and the first transistor and the second transistor overlap with each other.
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Citations
15 Claims
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1. A display device comprising:
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a driver circuit comprising a plurality of pulse output circuits, each of the plurality of pulse output circuits comprising a first transistor; and a pixel circuit comprising a second transistor and a third transistor, wherein each of the plurality of pulse output circuits is configured to drive a gate line, wherein the pixel circuit is electrically connected to the gate line, wherein a second layer comprising the second transistor is stacked over a first layer comprising the first transistor and the third transistor, wherein the first transistor and the second transistor overlap with each other, wherein the second transistor is electrically connected to the first transistor through a conductive layer provided in an opening of an insulating layer, wherein the insulating layer is sandwiched between the first transistor and the second transistor, wherein a gate electrode of the second transistor and a gate electrode of the third transistor are directly connected to the gate line, and wherein one of a source and a drain of the third transistor in the first layer is electrically connected to the second transistor in the second layer. - View Dependent Claims (2, 3, 4)
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5. A display device comprising:
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a driver circuit comprising a plurality of pulse output circuits, each of the plurality of pulse output circuits comprising a first transistor; a pixel circuit comprising a second transistor and a third transistor; and a display element electrically connected to the pixel circuit, wherein each of the plurality of pulse output circuits is configured to drive a gate line, wherein the pixel circuit is electrically connected to the gate line, wherein a second layer comprising the second transistor is stacked over a first layer comprising the first transistor and the third transistor, wherein the first transistor and the second transistor overlap with each other, wherein the second transistor is electrically connected to the first transistor through a conductive layer provided in an opening of an insulating layer, wherein the insulating layer is sandwiched between the first transistor and the second transistor, wherein a third layer comprising the display element is stacked over the second layer, wherein one of a source and a drain of the third transistor in the first layer is electrically connected to the second transistor in the second layer and the display element in the third layer, wherein a gate electrode of the second transistor and a gate electrode of the third transistor are directly connected to the gate line, and wherein the other of the source and the drain of the third transistor in the first layer is electrically connected to a monitor line in the first layer. - View Dependent Claims (6, 7, 8, 9)
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10. A display device comprising:
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a driver circuit comprising a plurality of pulse output circuits, each of the plurality of pulse output circuits comprising a first transistor; a pixel circuit comprising a second transistor and a third transistor; and a display element electrically connected to the pixel circuit, wherein each of the plurality of pulse output circuits is configured to drive a gate line, wherein the pixel circuit is electrically connected to the gate line, wherein a second layer comprising the second transistor is stacked over a first layer comprising the first transistor and the third transistor, wherein the first transistor and the second transistor overlap with each other, wherein the second transistor is electrically connected to the first transistor through a conductive layer provided in an opening of an insulating layer, wherein the insulating layer is sandwiched between the first transistor and the second transistor, wherein a third layer comprising the display element is stacked over the second layer, wherein one of a source and a drain of the third transistor in the first layer is electrically connected to the second transistor in the second layer and the display element in the third layer, wherein the other of the source and the drain of the third transistor in the first layer is electrically connected to a monitor line in the first layer, wherein a gate electrode of the second transistor and a gate electrode of the third transistor are directly connected to the gate line, and wherein a channel formation region of each of the first transistor and the second transistor comprises a metal oxide. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification