Method of manufacturing silicon carbide semiconductor device

• US 10,586,703 B2
• Filed: 05/17/2018
• Issued: 03/10/2020
• Est. Priority Date: 02/01/2016
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Wakimoto, Setsuko, Iwaya, Masanobu
• Primary Examiner(s): Wilczewski, Mary A
• Application Number:
  US15/982,543
• Publication Number:
  US 20180269064A1
• Time in Patent Office: 663 Days
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type

Abstract

In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.

Claims

1. A method of manufacturing a silicon carbide semiconductor device, the method comprising:

forming a first epitaxial layer of a first conductivity type on a front surface of a silicon carbide substrate;

selectively forming a fourth semiconductor region of a second conductively type within the first epitaxial layer;

forming, in the first epitaxial layer, a third semiconductor region of the first conductivity type having an impurity concentration greater than an impurity concentration of the first epitaxial layer, a bottom of the third semiconductor region being closer to a rear surface of the silicon carbide substrate than is a bottom of the fourth semiconductor region;

epitaxially growing a second epitaxial layer of a second conductivity type on the first epitaxial layer;

selectively forming a first semiconductor region of the second conductivity type by ion implantation in the second epitaxial layer, the first semiconductor region having an impurity concentration higher than that of the second epitaxial layer;

selectively forming a second semiconductor region of the first conductivity type in the second epitaxial layer, at a depth shallower than the first semiconductor region;

forming a trench to penetrate the second semiconductor region, the first semiconductor region, and the second epitaxial layer, and reach the fourth semiconductor region of the first epitaxial layer;

forming a gate insulating film in the trench;

forming a gate electrode in the trench such that the gate electrode is surrounded in the trench by the gate insulating film;

forming a first electrode contacting the second semiconductor region and the second epitaxial layer; and

forming a second electrode on the rear surface of the silicon carbide substrate, wherein

the first semiconductor region is formed to have a second-conductivity-type impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration higher than that of the second epitaxial layer.

2. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein

the first semiconductor region is formed by a plurality of stages of ion implantation to have the second-conductivity-type impurity concentration profile in which the concentration differences in the depth direction form a plurality of bell-shape curves at a plurality of peaks of impurity concentration higher than that of the second epitaxial layer.

3. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein

the ion implantation is performed using an accelerating voltage so that the peak of the impurity concentration in the second-conductivity-type impurity concentration profile is formed at a position deeper than an ion implantation surface.

4. The method of manufacturing a silicon carbide semiconductor device according to claim 1, comprising

forming a third epitaxial layer of the second conductivity type on the second epitaxial layer after forming the first semiconductor region and before forming the second semiconductor region.

5. The method of manufacturing a silicon carbide semiconductor device according claim 4, wherein

the ion implantation is performed using an accelerating voltage so that the peak of the impurity concentration in the second-conductivity-type impurity concentration profile is formed at a position equal to or deeper than an ion implantation surface.

6. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein

the ion implantation is performed using an accelerating voltage so that the peak of the impurity concentration in the second-conductivity-type impurity concentration profile is formed at a depth position farther on a first electrode side than a border of the second epitaxial layer and the first epitaxial layer.

7. A method of manufacturing a silicon carbide semiconductor device, the method comprising:

forming a first semiconductor layer of a first conductivity type on a front surface of a silicon carbide substrate;

selectively forming a fourth semiconductor region of a second conductively type within the first semiconductor layer;

forming, in the first semiconductor layer, a third semiconductor region of the first conductivity type having an impurity concentration greater than an impurity concentration of the first semiconductor layer, a bottom of the third semiconductor region being closer to a rear surface of the silicon carbide substrate than is a bottom of the fourth semiconductor region;

forming a second semiconductor layer of a second conductivity type on the first semiconductor layer;

selectively forming a first semiconductor region of the second conductivity type in the second semiconductor layer by ion implantation;

selectively forming a second semiconductor region of the first conductivity type in the second semiconductor layer, at a depth shallower than the first semiconductor region;

forming a trench to penetrate the second semiconductor region, the first semiconductor region, and the second semiconductor layer, and to reach the fourth semiconductor region;

forming a gate insulating film in the trench;

forming a gate electrode in the trench such that the gate electrode is surrounded in the trench by the gate insulating film;

forming a first electrode contacting the second semiconductor region and the second semiconductor layer; and

forming a second electrode on the rear surface of the silicon carbide substrate, wherein

the first semiconductor region is formed by a plurality of stages of ion implantation to have a second-conductivity-type impurity concentration profile in which concentration differences in a depth direction form a plurality of bell-shape curves at a plurality of peaks.

8. The method of manufacturing a silicon carbide semiconductor device according to claim 7, wherein

the first semiconductor region is formed to have the second-conductivity-type impurity concentration profile in which among the plurality of peaks, an impurity concentration at a first peak on a first electrode side is higher than that at a second peak on a second electrode side.