Buried power rails

• US 10,586,765 B2
• Filed: 06/18/2018
• Issued: 03/10/2020
• Est. Priority Date: 06/22/2017
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Smith, Jeffrey, Devilliers, Anton J., Tapily, Kandabara
• Primary Examiner(s): Anya, Igwe U
• Application Number:
  US16/011,377
• Publication Number:
  US 20180374791A1
• Time in Patent Office: 631 Days
• Field of Search: 257508
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 : for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/456 : on silicon
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Aspects of the disclosure provide a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a power rail formed in an isolation trench. The power rail is covered by a dielectric cap that isolates the power rail from conductive pattern structures on the dielectric cap. Further, an opening is selectively formed in the dielectric cap and is filled with conductive material to selectively connect a conductive pattern structure with the power rail.

Claims

1. A semiconductor device, comprising:

a first power rail formed in a first rail opening within a first isolation trench;

a first dielectric cap on the first power rail within the first rail opening, the first dielectric cap isolating the first power rail from a conductive pattern structure on the first dielectric cap;

a second power rail having substantially a same thickness as the first power rail and being formed in a second rail opening within a second isolation trench;

a second dielectric cap on the second power rail within the second rail opening, the second dielectric cap being etch-selective to a side material of the second rail opening; and

an opening formed by etching the second dielectric cap that is etch-selective to the side material of the second rail opening and resulting in the opening having a side aligned with the second power rail, the opening being filled with conductive material that connects the conductive pattern structure with the second power rail.

2. The semiconductor device of claim 1, wherein the first power rail is formed within the first isolation trench, and the second power rail is formed within the second isolation trench.

3. The semiconductor device of claim 1, wherein the first power rail is formed through the first isolation trench and into a bulk silicon substrate, and the second power rail is formed through the second isolation trench and into the bulk silicon substrate.

4. The semiconductor device of claim 1, wherein the second dielectric cap is of a material that is etch selective to a SiO liner between the second power rail and the second isolation trench and oxide in the second isolation trench.

5. The semiconductor device of claim 1, wherein the first dielectric cap is selective-deposited on the first power rail.

6. The semiconductor device of claim 1, wherein the first and second power rails are formed of a metal material that has a thermal stability over 700°

C.

7. The semiconductor device of claim 6, wherein the metal material is a refractive metal.

8. The semiconductor device of claim 7, wherein the first and second power rails are formed by filling the first and second rail openings with the refractive metal and etching back the refractive metal to a specific depth.

9. The semiconductor device of claim 6, wherein the metal material includes ruthenium.

10. The semiconductor device of claim 1, wherein an aspect ratio of the first and second power rails is pre-determined to meet a resistivity requirement of the first and second power rails.

11. The semiconductor device of claim 10, wherein a critical dimension width of the first and second power rails is pre-determined in conjunction with the aspect ratio.

12. A method for manufacturing a semiconductor device, comprising:

forming, in a first rail opening in first isolation trench, a first power rail and in a second rail opening in a second isolation trench, a second power rail having substantially a same thickness as the first power rail;

top-covering the first power rail with a first dielectric cap and the second power rail with a second dielectric cap, the second dielectric cap being etch-selective to a side material of the second rail opening; and

etching an opening in the second dielectric cap that is etch-selective to the side material of the second rail opening, and resulting in a side of the opening aligned with the second power rail;

filling the opening with conductive material to connect a conductive pattern structure with the second power rail through the filled opening, the first dielectric cap isolating the first power rail from the conductive pattern structure.

13. The method of claim 12, wherein forming, in the first rail opening in the first isolation trench, the first power rail and in the second rail opening in the second isolation trench, the second power rail further comprises:

etching the first rail opening within the first isolation trench and the second rail opening within the second isolation trench; and

forming the first power rail in the first rail opening within the first isolation trench, and the second power rail in the second rail opening within the second isolation trench.

14. The method of claim 12, wherein forming, in the first rail opening in the first isolation trench, the first power rail and in the second rail opening in the second isolation trench, the second power rail further comprises:

etching the first rail opening through the first isolation trench and into a bulk silicon substrate, and the second rail opening through the second isolation trench and into the bulk silicon substrate; and

forming the first power rail in the first rail opening that is in the first isolation trench and the bulk silicon substrate, and the second power rail in the second rail opening that is in the second isolation trench and the bulk silicon substrate.

15. The method of claim 12, wherein top-covering the first power rail with the first dielectric cap within the first isolation trench further comprises:

selective-depositing a dielectric material as the first dielectric cap that is etch selective to a SiO liner between the first power rail and the first isolation trench.

16. The method of claim 12, wherein forming, in the first rail opening in the first isolation trench, the first power rail and in the second rail opening in the second isolation trench, the second power rail further comprises:

forming the first power rail and the second power rail using a metal material that has a thermal stability over 700°

C.

17. The method of claim 16, wherein forming the first power rail and the second power rail using the metal material that has the thermal stability over 700°

C. further comprises;

forming the first power rail and the second power rail using ruthenium.

18. The method of claim 17, wherein forming the first power rail and the second power rail using ruthenium further comprises:

filling the first rail opening in the first isolation trench and the second rail opening in the second isolation trench with the ruthenium; and

etching back the ruthenium to a specific depth.

19. The method of claim 12, wherein forming, in the first rail opening in the first isolation trench, the first power rail and in the second rail opening in the second isolation trench, the second power rail further comprises:

forming a power rail that includes two rail lines.

20. The method of claim 19, wherein forming the power rail that includes the two rail lines further comprises:

conformally depositing a spacer layer on sidewalls and bottom of a rail opening in an isolation trench;

filling the rail opening with a dielectric material;

removing the spacer layer formed on sidewalls of the rail opening to form two spacer-trenches;

filling the two spacer-trenches with ruthenium; and

etching back the ruthenium to a specific depth.