Nanosheet FET device with epitaxial nucleation

• US 10,586,856 B2
• Filed: 06/14/2018
• Issued: 03/10/2020
• Est. Priority Date: 06/14/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Loubet, Nicolas, Frougier, Julien, Xu, Wenyu, Bi, Zhenxing
• Primary Examiner(s): Kim, Su C
• Application Number:
  US16/009,196
• Publication Number:
  US 20190386113A1
• Time in Patent Office: 635 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device is described. The semiconductor device includes a nanosheet stack including a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet. The semiconductor device includes a gate formed in a direction orthogonal to the plane of the nanosheet stack, with a gate spacer positioned along a sidewall of the gate. The semiconductor device includes an inner spacer liner deposited around the nanosheet stack and the gate spacer. A first etching of the inner spacer liner is configured to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet. A second etching of the inner spacer liner is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet.

Claims

1. A semiconductor device comprising:

a nanosheet stack comprising a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet;

a gate formed in a direction orthogonal to the plane of the nanosheet stack, a gate spacer positioned along a sidewall of the gate; and

an inner spacer liner deposited around the nanosheet stack and the gate spacer,

wherein a first etching of the inner spacer liner is configured to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet,

wherein a second etching of the inner spacer liner is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet, and

wherein following the second etching, a third etching is configured to remove the material of the inner spacer liner from a top surface and a bottom surface adjacent to the edge of the channel nanosheet.

2. The semiconductor device of claim 1, wherein the third etching comprises a lateral recess over etch process, and wherein the third etching is performed by continuing the second etching.

3. The semiconductor device of claim 1, wherein the third etching comprises a lateral recess over etch process, and wherein the third etching is performed using an isotropic etch process configured to use diluted chemistry relative to the second etching.

4. The semiconductor device of claim 1, wherein the third etching comprises a lateral recess over etch process, and wherein the third etching is performed using an isotropic etch process configured to use changed chemistry relative to the second etching.

5. The semiconductor device of claim 1, wherein the first etching is performed using an anisotropic dry etch process.

6. The semiconductor device of claim 1, wherein the second etching is performed using one of (i) an isotropic wet etch process and (ii) an isotropic dry etch process.

7. A method comprising:

forming a nanosheet stack comprising a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet;

forming a gate positioned in a direction orthogonal to the plane of the nanosheet stack, a gate spacer positioned along a sidewall of the gate;

depositing an inner spacer liner around the substrate, the nanosheet stack, and the gate spacer;

first etching, following the depositing, the inner spacer liner to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet;

second etching the inner spacer liner, wherein the second etching is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet;

then, performing epitaxial nucleation to bond the exposed portion of the channel nanosheet to an epitaxial layer; and

following the second etching, third etching to remove the material of the inner spacer liner from a top surface and a bottom surface adjacent to the edge of the channel nanosheet.

8. The method of claim 7, wherein the third etching comprises a lateral recess over etch process, and wherein the third etching is performed by continuing the second etching.

9. The method of claim 7, wherein the third etching comprises a lateral recess over etch process, and wherein the third etching is performed using an isotropic etch process configured to use diluted chemistry relative to the second etching.

10. The method of claim 7, wherein the third etching comprises a lateral recess over etch process, and wherein the third etching is performed using an isotropic etch process configured to use changed chemistry relative to the second etching.

11. The method of claim 7, wherein the first etching is performed using an anisotropic dry etch process.

12. The method of claim 7, wherein the second etching is performed using one of (i) an isotropic wet etch process and (ii) an isotropic dry etch process.

13. A semiconductor fabrication system comprising a processor, a computer-readable memory, and a computer-readable storage device, and program instructions stored on the storage device for execution by the processors via the memories, the stored program instructions causing the fabrication system to perform operations comprising:

forming a nanosheet stack comprising a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet;

forming a gate formed in a direction orthogonal to the plane of the nanosheet stack, a gate spacer positioned along a sidewall of the gate; and

forming an inner spacer liner deposited around the nanosheet stack and the gate spacer,

wherein a first etching of the inner spacer liner is configured to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet,

wherein a second etching of the inner spacer liner is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet, and

wherein following the second etching, a third etching is configured to remove the material of the inner spacer liner from a top surface and a bottom surface adjacent to the edge of the channel nanosheet.

14. The semiconductor fabrication system of claim 13, wherein the third etching comprises a lateral recess over etch process, and wherein the third etching is performed by continuing the second etching.

15. The semiconductor fabrication system of claim 13, wherein the third etching comprises a lateral recess over etch process, and wherein the third etching is performed using an isotropic etch process configured to use diluted chemistry relative to the second etching.

16. The semiconductor fabrication system of claim 13, wherein the third etching comprises a lateral recess over etch process, and wherein the third etching is performed using an isotropic etch process configured to use changed chemistry relative to the second etching.

17. The semiconductor fabrication system of claim 13, wherein the first etching is performed using an anisotropic dry etch process.