Transient stabilized cascode biasing
First Claim
1. A circuit arrangement comprising:
- a stacked cascode amplifier comprising an input transistor and one or more cascode transistors, the one or more cascode transistors comprising an output transistor, wherein the input transistor is configured to receive an RF signal and the output transistor is configured to output an amplified version of the RF signal;
a reference circuit that is a scaled down version of the stacked cascode amplifier, the reference circuit coupled to the stacked cascode amplifier via respective gate nodes; and
a biasing circuit configured to provide a biasing voltage to at least one gate node of a transistor of the one or more cascode transistors and a gate node of a respective transistor of the reference circuit,wherein the biasing circuit comprises a feedback loop that senses a voltage at a source node of the respective transistor of the reference circuit and controls the biasing voltage so that a sensed voltage at said source node is equal to a reference voltage,wherein the feedback loop comprises an operational amplifier comprising a positive input coupled to the reference voltage, a negative input coupled to the source node of the respective transistor of the reference circuit, and an output coupled to the at least one gate node, andwherein the reference voltage is generated via a resistive voltage divider comprising two series connected resistors with configurable resistances.
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Accused Products
Abstract
A biasing circuit with high current drive capability for fast settling of a biasing voltage to a stacked cascode amplifier is presented. According to a first aspect, the biasing circuit uses transistors matched with transistors of the cascode amplifier to generate a boost current during a transition phase that changes the biasing voltage by charging or discharging a capacitor. The boost current is activated during the transition phase and deactivated when a steady-state condition is reached. According to a second aspect, the biasing circuit uses an operational amplifier in a feedback loop that forces a source node of a cascode transistor of a reference circuit, that is a scaled down replica version of the cascode amplifier, to be at a reference voltage. The high gain and high current capability of the operational amplifier, provided by isolating a high frequency signal processed by the cascode amplifier from the reference circuit, allow for a quick settling of the biasing voltage.
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Citations
36 Claims
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1. A circuit arrangement comprising:
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a stacked cascode amplifier comprising an input transistor and one or more cascode transistors, the one or more cascode transistors comprising an output transistor, wherein the input transistor is configured to receive an RF signal and the output transistor is configured to output an amplified version of the RF signal; a reference circuit that is a scaled down version of the stacked cascode amplifier, the reference circuit coupled to the stacked cascode amplifier via respective gate nodes; and a biasing circuit configured to provide a biasing voltage to at least one gate node of a transistor of the one or more cascode transistors and a gate node of a respective transistor of the reference circuit, wherein the biasing circuit comprises a feedback loop that senses a voltage at a source node of the respective transistor of the reference circuit and controls the biasing voltage so that a sensed voltage at said source node is equal to a reference voltage, wherein the feedback loop comprises an operational amplifier comprising a positive input coupled to the reference voltage, a negative input coupled to the source node of the respective transistor of the reference circuit, and an output coupled to the at least one gate node, and wherein the reference voltage is generated via a resistive voltage divider comprising two series connected resistors with configurable resistances. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method for biasing a stacked cascode amplifier, the method comprising:
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providing a reference circuit that is a scaled down version of the stacked cascode amplifier; coupling gate nodes of the stacked cascode amplifier to respective gate nodes of the reference circuit via respective resistors; based on the coupling, isolating an RF signal processed by the stacked cascode amplifier from the reference circuit; and controlling, via a feedback loop with higher gain, a biasing voltage to a gate node of a cascode transistor of the stacked cascode amplifier based on a voltage sensed at a source node of a respective transistor of the reference circuit, wherein the higher gain is provided by the isolating, wherein the feedback loop controls the biasing voltage so that the voltage sensed at said source node is equal to a reference voltage, wherein the feedback loop comprises an operational amplifier comprising a positive input coupled to the reference voltage, a negative input coupled to the source node of the respective transistor of the reference circuit, and an output coupled to the at least one gate node, and wherein the reference voltage is generated via a resistive voltage divider comprising two series connected resistors with configurable resistances.
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19. A circuit arrangement comprising:
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a stacked cascode amplifier comprising an input transistor and one or more cascode transistors, the one or more cascode transistors comprising an output transistor, wherein the input transistor is configured to receive an RF signal and the output transistor is configured to output an amplified version of the RF signal; a reference circuit that is a scaled down version of the stacked cascode amplifier, the reference circuit coupled to the stacked cascode amplifier via respective gate nodes; and a biasing circuit configured to provide a biasing voltage to at least one gate node of a transistor of the one or more cascode transistors and a gate node of a respective transistor of the reference circuit, wherein; the biasing circuit comprises a feedback loop that senses a voltage at a source node of the respective transistor of the reference circuit and controls the biasing voltage so that a sensed voltage at said source node is equal to a reference voltage, the one or more cascode transistors comprises a plurality of cascode transistors, the biasing circuit is further configured to provide an additional biasing voltage to a gate node of an additional transistor of the plurality of cascode transistors and a gate node of a respective additional transistor of the reference circuit, and the biasing circuit further comprises an additional feedback loop that senses a voltage at a source node of the respective additional transistor of the reference circuit and controls the additional biasing voltage so that a sensed voltage at said source node is equal to an additional reference voltage. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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Specification