Digital signal processing device of base station and method for processing data thereof

• US 10,588,080 B2
• Filed: 07/30/2018
• Issued: 03/10/2020
• Est. Priority Date: 03/27/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Yonghae, Kim, Hanseok, Park, Seongyong, Won, Jeongjae, Lee, Junsung
• Primary Examiner(s): Jung, Min
• Application Number:
  US16/049,186
• Publication Number:
  US 20180338279A1
• Time in Patent Office: 589 Days
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H04L 5/0048 Allocation of pilot signals, i.e. of signals known to the receiver
• CPC Class Codes: H04W 52/0206 in access points, e.g. base stations access point devices per se H04W88/08
• CPC Class Codes: H04W 52/0225 using monitoring of external events, e.g. the presence of a signal
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A digital signal processing device of a base station configured to process down-link signals in a wireless communication system employing orthogonal frequency division multiple access (OFDMA) and a method of processing data in the device are provided. The device includes a clock controller configured to monitor whether a signal is allocated to an input and control a frequency of clocks to have a first or second characteristic based on the monitored result, and a data processor configured to process the input, and synchronize with the clock controlled by the clock controller.

Claims

1. A device of a base station, configured to process down-link signals in a wireless communication system employing orthogonal frequency division multiple access (OFDMA), the device comprising:

a clock controller; and

a data processor,

wherein the clock controller is configured to;

identify whether inphase/quadrature (IQ) data modulated from user data for a terminal is detected from an input signal entered into the data processor, and

determine a frequency of clocks as a first frequency, if the IQ data modulated from the user data is detected from the input signal or the frequency of clocks as a second frequency, if the IQ data modulated from the user data is not detected from the input signal, based on the identified result, and

wherein the data processor is configured to synchronize the input signal using the determined frequency of clocks.

2. The device of claim 1, wherein the first frequency is greater than the second frequency.

3. The device of claim 1, wherein the input signal includes at least one reference signal and IQ data modulated from control data for the terminal.

4. The device of claim 1, wherein, after the IQ data modulated from the user data is detected within a first symbol of the input signal, if the IQ data modulated from the user data is not detected within a second symbol of the input signal until a period of time has elapsed, the clock controller is further configured to control the frequency of the clocks to the second frequency.

5. The device of claim 4, wherein the period of time is set, considering at least one of a time of stabilization according to on-off operation of the data processor and a time for processing user data of the data processor.

6. The device of claim 1, wherein the clock controller is further configured to monitor an amount of the IQ data modulated from the user data and scale the first frequency based on the amount of the IQ data modulated from the user data.

7. A digital signal processing device of a base station, configured to process down-link signals in a wireless communication system employing orthogonal frequency division multiple access (OFDMA), the device comprising:

a buffer configured to buffer an input signal;

a clock controller configured to;

identify whether inphase/quadrature (IQ) data modulated from user data for a terminal is detected from the input signal,

determine a first clock corresponding to a first frequency, if the IQ data modulated from the user data is detected from the input signal or a second clock corresponding to a second frequency, if the IQ data modulated from the user data is not detected from the input signal, based on the identified result, and

generate a clock selection control signal based on the determined clock;

a clock providing unit configured to provide the first clock and the second clock;

a multiplexer configured to output the first clock or the second clock in response to the clock selection control signal; and

a data processor configured to synchronize the input signal buffered in the buffer using the output clock from the multiplexer.

8. The device of claim 7, wherein the first frequency is greater than the second frequency.

9. The device of claim 7, wherein the input signal includes at least one reference signal and IQ data modulated from control data for the terminal.

10. The device of claim 7, wherein, after the IQ data modulated from the user data is detected within a first symbol of the input signal, if the IQ data modulated from the user data is not detected within a second symbol of the input signal until a period of time has elapsed, the clock controller is further configured to generate the clock selection control signal to select the second clock by the multiplexer.

11. The device of claim 10, wherein the period of time is set, considering at least one of a time of stabilization according to on-off operation of the data processor and a time for processing user data of the data processor.

12. The device of claim 11, wherein the buffer is further configured to delay the received input signal based on the time of stabilization according to on-off operation of the data processor.

13. The device of claim 7, wherein the clock controller is further configured to:

monitor an amount of the IQ data modulated from the user data, and

scale the first frequency based on the amount of the IQ data modulated from the user data.

14. A method of processing data in a digital signal processing device of a base station, configured to process down-link signals in a wireless communication system employing orthogonal frequency division multiple access (OFDMA), the method comprising:

modulating user data for a terminal to inphase/quadrature (IQ) data;

identifying whether the IQ data modulated from the user data is detected from an input signal entered into a data processor configured to process the user data;

providing, if the IQ data modulated from the user data is detected from the input signal, a first clock corresponding to a first frequency to the data processor; and

providing, if the IQ data modulated from the user data is not detected from the input signal, a second clock corresponding to a second frequency to the data processor.

15. The method of claim 14, wherein the first frequency is greater than the second frequency.

16. The method of claim 14, further comprising:

modulating control data for the terminal to inphase/quadrature (IQ) data.

17. The method of claim 15, wherein the input signal includes at least one reference signal and the IQ data modulated from the control data.

18. The method of claim 14, further comprising:

providing the second clock to the data processor, after the IQ data modulated from the user data is detected within a first symbol of the input signal, if the IQ data modulated from the user data is not detected within a second symbol of the input signal until a period of time.

19. The method of claim 14, wherein the period of time is set, considering at least one of a time of stabilization according to on-off operation of the data processor and a time for processing the user data of the data processor.

20. The method of claim 14, further comprising:

monitoring an amount of the IQ data modulated from the user data when the IQ data modulated from the user data is detected from the input signal; and

scaling the first frequency based on the amount of the IQ data modulated from the user data.