Compressed scan chains with three input mask gates and registers

• US 10,591,540 B2
• Filed: 03/19/2018
• Issued: 03/17/2020
• Est. Priority Date: 06/11/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Narayanan, Prakash, Parekhji, Rubin A., Jain, Arvind, Subramanian, Sundarrajan
• Primary Examiner(s): Mehrmanesh, Elmira
• Application Number:
  US15/925,200
• Publication Number:
  US 20180210030A1
• Time in Patent Office: 729 Days
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Claims

1. An electronic scan circuitry comprising:

(a) decompressor circuitry having a serial data input line and parallel data output lines;

(b) scan chains, each scan chain having a scan chain input coupled to one parallel data output line and having a scan chain output;

(c) first masking circuitry having first masking inputs coupled to a first group of the scan chain outputs, the first masking circuitry including;

(i) first gates, each first gate having a first input connected to a first masking input, a second input coupled to a first qualify line, a third input, and a first masking output; and

(ii) first registers coupled in series, each first register having a serial input and an output connected to the third input of a first gate;

(d) second masking circuitry having second masking inputs coupled to a second group of the scan chain outputs, the second masking circuitry including;

(i) second gates, each second gate having a first input connected to a second masking input, a second input coupled to a second qualify line separate from the first qualify line, a third input, and a second masking output; and

(ii) second registers coupled in series with the first registers, each second register having a serial input and an output connected to a third input of the second gates; and

(e) compactor circuitry having parallel compactor inputs coupled to the first masking outputs and the second masking outputs, and having a serial compactor output.

2. The electronic scan circuitry of claim 1 including scannable masking qualification circuitry having a serial output coupled to the serial inputs of the first and second registers.

3. The electronic scan circuitry of claim 1 including scannable masking qualification circuitry having the first qualify line coupled to the second inputs of the first gates and the second qualify line coupled to the second inputs of the second gates.

4. The electronic scan circuitry of claim 1 in which the scannable masking qualification circuit includes a chain shift register having a serial input, a serial output coupled with a serial input of the second registers, and a set of shift register cells coupled between the serial input and serial output.

5. The electronic scan circuitry of claim 4 in which the serial input of the chain shift register is coupled to a parallel data output line of the decompressor circuitry.

6. The electronic scan circuitry of claim 1 in which the scannable masking qualification circuit includes multiplexer circuitry having separate qualify lines coupled to the second inputs of the first and second gates, having a control input, and including generator circuitry having an output coupled to the control input of the multiplexer circuitry.

7. The electronic scan circuitry of claim 1 including scan circuitry having a clock signal input and a scan output coupled to the scan chains.

8. The electronic scan circuitry of claim 1 in which there are eight first gates and eight second gates.