Semiconductor device and electronic device

• US 10,591,791 B2
• Filed: 04/11/2016
• Issued: 03/17/2020
• Est. Priority Date: 04/20/2015
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Fukutome, Takahiro
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US15/563,663
• Publication Number:
  US 20180095336A1
• Time in Patent Office: 1,436 Days
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A semiconductor device with an improved aperture ratio is provided. Furthermore, a semiconductor device having lower power consumption is provided. The semiconductor device includes a first wiring, a second wiring, a third wiring, a first driver circuit, a second driver circuit, and a cell array, and the cell array includes a plurality of cells each including a transistor and a storage capacitor. The first wiring is electrically connected to the first driver circuit, the second wiring is electrically connected to the second driver circuit, the transistor is positioned above the second wiring, the second wiring includes a region serving as a first gate electrode of the transistor in a region overlapping with the transistor, the third wiring is positioned above the transistor and includes a region overlapping with the second wiring, and the second wiring is electrically connected to the third wiring in a region outside the cell array.

Claims

1. A semiconductor device comprising:

a first driver circuit;

a second driver circuit;

a first wiring electrically connected to the first driver circuit;

a second wiring electrically connected to the second driver circuit;

a third wiring; and

a cell array comprising a plurality of cells,

wherein a first cell in the plurality of cells comprises a transistor comprising a first gate electrode, an oxide semiconductor film, and a second gate electrode,

wherein the second wiring serves as the first gate electrode,

wherein the third wiring serves as the second gate electrode,

wherein the second wiring is electrically connected to the third wiring through a first contact hole outside the cell array, and

wherein the second wiring is electrically connected to the third wiring through a second contact hole inside the cell array.

2. The semiconductor device according to claim 1,

wherein the first contact hole is in a region between the cell array and the second driver circuit.

3. The semiconductor device according to claim 2,

wherein a width of the second wiring in the region is larger than a width of the second wiring overlapping with the cell array.

4. The semiconductor device according to claim 1,

wherein electric resistance of the third wiring is lower than or equal to electric resistance of the second wiring.

5. The semiconductor device according to claim 1,

wherein the third wiring comprises copper.

6. The semiconductor device according to claim 1,

wherein the first cell is a pixel, and

wherein the cell array is a pixel portion.

7. An electronic device comprising the semiconductor device according to claim 1.

8. A semiconductor device comprising:

a first driver circuit;

a second driver circuit;

a third driver circuit;

a first wiring electrically connected to the first driver circuit;

a second wiring electrically connected to one of the second driver circuit and the third driver circuit;

a third wiring; and

a cell array comprising a plurality of cells, the cell array being between the second driver circuit and the third driver circuit,

wherein a first cell in the plurality of cells comprises a transistor comprising a first gate electrode, an oxide semiconductor film, and a second gate electrode,

wherein the second wiring serves as the first gate electrode,

wherein the third wiring serves as the second gate electrode,

wherein the second wiring is electrically connected to the third wiring through a first contact hole outside the cell array, and

wherein the second wiring is electrically connected to the third wiring through a second contact hole inside the cell array.

9. The semiconductor device according to claim 8,

wherein the first contact hole is in a region between the cell array and the second driver circuit.

10. The semiconductor device according to claim 9,

wherein a width of the second wiring in the region is larger than a width of the second wiring overlapping with the cell array.

11. The semiconductor device according to claim 8,

wherein electric resistance of the third wiring is lower than or equal to electric resistance of the second wiring.

12. The semiconductor device according to claim 8,

wherein the third wiring comprises copper.

13. The semiconductor device according to claim 8,

wherein the first cell is a pixel, and

wherein the cell array is a pixel portion.

14. An electronic device comprising the semiconductor device according to claim 8.

15. A semiconductor device comprising:

a first driver circuit;

a second driver circuit;

a first wiring electrically connected to the first driver circuit;

a second wiring electrically connected to the second driver circuit;

a third wiring; and

a cell array comprising a plurality of cells,

wherein a first cell in the plurality of cells comprises a transistor comprising a first gate electrode, an oxide semiconductor film, and a second gate electrode,

wherein the second wiring serves as the first gate electrode,

wherein the third wiring serves as the second gate electrode,

wherein the second wiring is electrically connected to the third wiring through a first contact hole outside the cell array,

wherein the first contact hole is in a region between the cell array and the second driver circuit, and

wherein a width of the second wiring in the region is larger than a width of the second wiring overlapping with the cell array.

16. A semiconductor device comprising:

a first driver circuit;

a second driver circuit;

a third driver circuit;

a first wiring electrically connected to the first driver circuit;

a second wiring electrically connected to one of the second driver circuit and the third driver circuit;

a third wiring; and

a cell array comprising a plurality of cells, the cell array being between the second driver circuit and the third driver circuit,

wherein a first cell in the plurality of cells comprises a transistor comprising a first gate electrode, an oxide semiconductor film, and a second gate electrode,

wherein the second wiring serves as the first gate electrode,

wherein the third wiring serves as the second gate electrode,

wherein the second wiring is electrically connected to the third wiring through a first contact hole outside the cell array,

wherein the first contact hole is in a region between the cell array and the second driver circuit, and

wherein a width of the second wiring in the region is larger than a width of the second wiring overlapping with the cell array.