Transducer clock signal distribution
First Claim
Patent Images
1. A method, comprising:
- receiving a clock signal at a first tile controller buffer of a plurality of tile controller buffers;
receiving the clock signal received at the first tile controller buffer at a second tile controller buffer and a third tile controller buffer at substantially the same time from the first tile controller buffer, the second tile controller buffer being horizontally adjacent to the first tile controller buffer and the third tile controller buffer being vertically adjacent to the first tile controller buffer; and
receiving the clock signal received at the first tile controller buffer at a fourth controller buffer from the first tile controller buffer and the clock signal received at the second tile controller buffer at the fourth tile controller buffer, the fourth tile controller buffer being horizontally adjacent to the third tile controller buffer and vertically adjacent to the second tile controller buffer.
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Abstract
An array of ultrasonic transducers can be controlled to produce a steerable beam. Beam steering can be skewed by buffer delays in the distribution of a clock signal. The skew can be at least approximately linearized by distributing the clock signal in a diagonal fashion across an array of buffers corresponding to ultrasonic transducer controllers. Potential error in beam steering that can arise from clock skew can be corrected based on the linear tilt.
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Citations
20 Claims
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1. A method, comprising:
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receiving a clock signal at a first tile controller buffer of a plurality of tile controller buffers; receiving the clock signal received at the first tile controller buffer at a second tile controller buffer and a third tile controller buffer at substantially the same time from the first tile controller buffer, the second tile controller buffer being horizontally adjacent to the first tile controller buffer and the third tile controller buffer being vertically adjacent to the first tile controller buffer; and receiving the clock signal received at the first tile controller buffer at a fourth controller buffer from the first tile controller buffer and the clock signal received at the second tile controller buffer at the fourth tile controller buffer, the fourth tile controller buffer being horizontally adjacent to the third tile controller buffer and vertically adjacent to the second tile controller buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system, comprising:
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a plurality of tile controller buffers; a clock signal generator; and a computer-implemented clock signal distributor that sends a clock signal from a first tile controller buffer of the plurality of tile controller buffers at substantially the same time to a second tile controller buffer and third tile controller buffer, the second tile controller buffer being horizontally adjacent to the first tile controller buffer and the third tile controller buffer being vertically adjacent to the first tile controller buffer, sends a clock signal received from the first tile controller buffer at the second tile controller buffer to a fourth tile controller buffer from the second tile controller buffer, the fourth tile controller buffer being vertically adjacent to the second tile controller buffer and horizontally adjacent to the third tile controller buffer, and sends a clock signal received from the first tile controller buffer at the third tile controller buffer to the fourth tile controller buffer from the third tile controller buffer. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method, comprising:
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receiving a clock signal at a first tile controller buffer of a plurality of tile controller buffers; receiving the clock signal received at the first tile controller buffer at a second tile controller buffer and a third tile controller buffer at substantially the same time from the first tile controller buffer, the second tile controller buffer being horizontally adjacent to the first tile controller buffer and the third tile controller buffer being vertically adjacent to the first tile controller buffer; and receiving the clock signal received at the first tile controller buffer at a fourth controller buffer from the first tile controller buffer and the clock signal received at the second tile controller buffer at the fourth tile controller buffer, the fourth tile controller buffer being horizontally adjacent to the third tile controller buffer and vertically adjacent to the second tile controller buffer.
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17. A method, comprising:
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receiving a clock signal at a first subarray controller buffer of a plurality of subarray controller buffers; receiving the clock signal received at the first subarray controller buffer at a second subarray controller buffer and a third subarray controller buffer at substantially the same time from the first subarray controller buffer, the second subarray controller buffer being horizontally adjacent to the first subarray controller buffer and the third subarray controller buffer being vertically adjacent to the first subarray controller buffer; and receiving the clock signal received at the first subarray controller buffer at a fourth controller buffer from the first subarray controller buffer and the clock signal received at the second subarray controller buffer at the fourth subarray controller buffer, the fourth subarray controller buffer being horizontally adjacent to the third subarray controller buffer and vertically adjacent to the second subarray controller buffer. - View Dependent Claims (18, 19, 20)
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Specification