Hierarchical pre-fetch pipelining in a hybrid memory server

• US 10,592,118 B2
• Filed: 02/21/2019
• Issued: 03/17/2020
• Est. Priority Date: 06/24/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Yuk Lung, Krishnamurthy, Rajaram B., Parris, Carl Joseph
• Primary Examiner(s): Bilgrami, Ashgar H
• Application Number:
  US16/281,211
• Publication Number:
  US 20190187895A1
• Time in Patent Office: 390 Days
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 16/172 Caching, prefetching or hoarding of files
• CPC Class Codes: G06F 16/182 Distributed file systems
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 2212/264 Remote server
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: H04L 41/5054 Automatic deployment of services triggered by the service manager, e.g. service implementation by automatic configuration of network components
• CPC Class Codes: H04L 47/24 Traffic characterised by specific attributes, e.g. priority or QoS
• CPC Class Codes: H04L 67/568 Storing data temporarily at an intermediate stage, e.g. caching

Abstract

A method, hybrid server system, and computer program product, prefetch data. A set of prefetch requests associated with one or more given datasets residing on the server system are received from a set of accelerator systems. A set of data is prefetched from a memory system residing at the server system for at least one prefetch request in the set of prefetch requests. The set of data satisfies the at least one prefetch request. The set of data that has been prefetched is sent to at least one accelerator system, in the set of accelerator systems, associated with the at least one prefetch request.

Claims

1. A method, with a server system in an out-of-core processing environment, comprising:

partitioning memory within the server system into a first set of memory managed by a plurality of accelerator systems and a second set of memory managed by the server system;

assigning different portions of memory within the server system to a plurality of accelerator systems, wherein the different portions of memory are to be managed by the plurality of accelerator systems; and

receiving data within the first set of memory, wherein the data is directly written into the first set of memory by at least one of the accelerator systems of the plurality of accelerator systems.

2. The method of claim 1, wherein the first set of memory is private to the plurality of accelerator systems.

3. The method of claim 1, further comprising:

releasing at least a portion of the second memory to one or more accelerator systems of the plurality of accelerator systems.

4. The method of claim 1, further comprising:

determining that an accelerator system of the plurality of accelerator systems has released a portion memory residing at the accelerator system; and

accessing, based on the determining, the portion of memory residing at the accelerator system.

5. The method of claim 1, further comprising:

disallowing access to the second set of memory by the plurality of accelerator systems.

6. The method of claim 1, wherein the partitioning comprises:

assigning, to each accelerator system of the plurality of accelerator systems, a portion of the first set of memory as private memory that is only accessible by the accelerator system.

7. The method of claim 6, wherein a remaining portion of the first of memory is accessible by all the accelerator systems of the plurality of accelerator systems.

8. A server system in an out-of-core processing environment, the server system comprising:

a memory;

a processor communicatively coupled to the memory; and

a data manager communicatively coupled to the memory and the processor, wherein the data manager is configured to perform;

partitioning memory within the server system into a first set of memory managed by a plurality of accelerator systems and a second set of memory managed by the server system;

assigning different portions of memory within the server system to a plurality of accelerator systems, wherein the different portions of memory are to be managed by the plurality of accelerator systems; and

receiving data within the first set of memory, wherein the data is directly written into the first set of memory by at least one of the accelerator systems of the plurality of accelerator systems.

9. The server system of claim 8, wherein the first set of memory is private to the plurality of accelerator systems.

10. The server system of claim 8, wherein the data manager is further configured to perform:

releasing at least a portion of the second memory to one or more accelerator systems of the plurality of accelerator systems.

11. The server system of claim 8, wherein the data manager is further configured to perform:

determining that an accelerator system of the plurality of accelerator systems has released a portion memory residing at the accelerator system; and

accessing, based on the determining, the portion of memory residing at the accelerator system.

12. The server system of claim 8, wherein the data manager is further configured to perform:

disallowing access to the second set of memory by the plurality of accelerator systems.

13. The server system of claim 8, wherein the partitioning comprises:

assigning, to each accelerator system of the plurality of accelerator systems, a portion of the first set of memory as private memory that is only accessible by the accelerator system, wherein a remaining portion of the first of memory is accessible by all the accelerator systems of the plurality of accelerator systems.

14. A computer program product for managing accelerator system access to data, the computer program product comprising a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:

partitioning memory within the server system into a first set of memory managed by a plurality of accelerator systems and a second set of memory managed by the server system;

assigning different portions of memory within the server system to a plurality of accelerator systems, wherein the different portions of memory are to be managed by the plurality of accelerator systems; and

receiving data within the first set of memory, wherein the data is directly written into the first set of memory by at least one of the accelerator systems of the plurality of accelerator systems.

15. The computer program product of claim 14, wherein the first set of memory is private to the plurality of accelerator systems.

16. The computer program product of claim 14, wherein the method further comprises:

releasing at least a portion of the second memory to one or more accelerator systems of the plurality of accelerator systems.

17. The computer program product of claim 14, wherein the method further comprises:

determining that an accelerator system of the plurality of accelerator systems has released a portion memory residing at the accelerator system; and

accessing, based on the determining, the portion of memory residing at the accelerator system.

18. The computer program product of claim 14, wherein the method further comprises:

disallowing access to the second set of memory by the plurality of accelerator systems.

19. The computer program product of claim 14, wherein the partitioning comprises:

assigning, to each accelerator system of the plurality of accelerator systems, a portion of the first set of memory as private memory that is only accessible by the accelerator system.

20. The computer program product of claim 19, wherein a remaining portion of the first of memory is accessible by all the accelerator systems of the plurality of accelerator systems.