Merging data from single-level cell block to multiple-level cell block using scrambler with different seeds

• US 10,592,157 B2
• Filed: 10/16/2018
• Issued: 03/17/2020
• Est. Priority Date: 11/13/2017
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: Lin, Wen-Sheng, Chen, Yu-Da
• Primary Examiner(s): Kim, Hong C
• Application Number:
  US16/161,900
• Publication Number:
  US 20190146705A1
• Time in Patent Office: 518 Days
• Field of Search: 711103, 711161, 713193
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A data storage device includes a memory device and a controller. The memory device includes multiple memory blocks. The memory blocks include single-level cell blocks and multiple-level cell blocks. The controller is coupled to the memory device. When the controller executes a predetermined procedure to write data stored in the single-level cell blocks into the multiple-level cell blocks, the controller is configured to determine whether a valid page count corresponding to each single-level cell block is greater than a threshold, and when the valid page count corresponding to more than one single-level cell block is greater than the threshold, the controller is configured to execute a first merge procedure to directly write the data stored in the single-level cell blocks with the valid page count greater than the threshold into one or more of the multiple-level cell blocks.

Claims

1. A data storage device, comprising:

a memory device, comprising a plurality of memory blocks, wherein the memory blocks comprise a plurality of single-level cell blocks and a plurality of multiple-level cell blocks, and wherein the single-level cell blocks comprise at least a first single-level cell block and a second single-level cell block; and

a controller, coupled to the memory device and comprising a scrambler and an encoder,

wherein when the controller receives first data to be written in the memory device from a host device, the scrambler is configured to perform data scrambling on the first data according to a first set of random seeds, the encoder is configured to encode the scrambled first data and the controller is configured to write the scrambled and encoded first data in the first single-level cell block, and

when the controller receives second data to be written in the memory device from the host device, the scrambler is configured to perform data scrambling on the second data according to a second set of random seeds, the encoder is configured to encode the scrambled second data and the controller is configured to write the scrambled and encoded second data in the second single-level cell block,

wherein the first set of random seeds and the second set of random seeds are different,

wherein in response to a valid page count corresponding to more than one single-level cell block being greater than a threshold, the controller is configured to execute a first merge procedure to directly write the data stored in the single-level cell blocks with the valid page count greater than the threshold into one or more of the multiple-level cell blocks,

wherein in response to the valid page count corresponding to one single-level cell block not being greater than the threshold, the controller is configured to execute a second merge procedure to determine whether data stored in physical pages of an single-level cell block is all valid,

wherein in response to the data stored in one physical page of the single-level cell block not being all valid, the controller is configured to read valid data of valid pages of the single-level cell block and store the valid data of the valid pages in a buffer,

wherein in response to the amount of valid data that can be written to a multiple-level cell block having been collected in the buffer, the valid data is written into one of the multiple-level cell blocks.

2. The data storage device as claimed in claim 1, wherein the single-level cell blocks further comprise a third single-level cell block, and when the controller receives third data to be written in the memory device from the host device, the scrambler is configured to perform data scrambling on the third data according to a third set of random seeds, the encoder is configured to encode the scrambled third data and the controller is configured to write the scrambled and encoded third data in the third single-level cell block.

3. The data storage device as claimed in claim 2, wherein the first set of random seeds, the second set of random seeds and the third set of random seeds each comprise a predetermined number of respective random seeds, and wherein the first set of random seeds, the second set of random seeds and the third set of random seeds are all different.

4. The data storage device as claimed in claim 1, wherein the data stored in different physical pages of the first single-level cell block are scrambled according to different random seeds in the first set of random seeds, the data stored in different physical pages of the second single-level cell block are scrambled according to different random seeds in the second set of random seeds, and wherein the scrambler is configured to store the random seed utilized for scrambling the data of each physical page in a spare region of the corresponding physical page.

5. The data storage device as claimed in claim 4, wherein when reading the first data, the controller is configured to read the first data from the memory device, the encoder is configured to decode the first data, and the scrambler is configured to descramble the decoded first data according to the corresponding random seed stored in the corresponding spare region to obtain the first data after being decoded and descrambled.

6. The data storage device as claimed in claim 2, wherein when the controller determines to perform a direct merge procedure to write the data stored in the single-level cell blocks to the multiple-level cell blocks, the controller is configured to sequentially read the data which is stored in the first single-level cell block, the second single-level cell block, and the third single-level cell block, and to sequentially write the data into one of the multiple-level cell blocks.

7. A method for processing data stored in a memory device, suitable for a data storage device, the data storage device comprising the memory device and a controller, the memory device comprising a plurality of memory blocks, the memory blocks comprising a plurality of single-level cell blocks and a plurality of multiple-level cell blocks, and the single-level cell blocks comprising at least a first single-level cell block and a second single-level cell block, the method comprising:

when writing first data in the memory device, scrambling the first data according to a first set of random seeds, encoding the scrambled first data and writing the scrambled and encoded first data in the first single-level cell block;

when writing second data in the memory device, scrambling the second data according to a second set of random seeds, encoding the scrambled second data and writing the scrambled and encoded second data in the second single-level cell block, wherein the first set of random seeds and the second set of random seeds are different;

in response to a valid page count corresponding to more than one single-level cell block being greater than a threshold, executing a first merge procedure to directly write the data stored in the single-level cell blocks with the valid page count greater than the threshold into one or more of the multiple-level cell blocks;

in response to the valid page count corresponding to one single-level cell block not being greater than the threshold, executing a second merge procedure to determine whether data stored in physical pages of an single-level cell block is all valid;

in response to the data stored in one physical page of the single-level cell block not being all valid, reading valid data of valid pages of the single-level cell block and storing the valid data of the valid pages in a buffer; and

in response to the amount of valid data that can be written to a multiple-level cell block having been collected in the buffer, writing the valid data into one of the multiple-level cell blocks.

8. The data storage device as claimed in claim 7, wherein the single-level cell blocks further comprise a third single-level cell block, and the method further comprises:

when writing third data in the memory device, scrambling the third data according to a third set of random seeds, encoding the scrambled third data and writing the scrambled and encoded third data in the third single-level cell block.

9. The method as claimed in claim 8, wherein the first set of random seeds, the second set of random seeds and the third set of random seeds each comprise a predetermined number of respective random seeds, and wherein the first set of random seeds, the second set of random seeds and the third set of random seeds are all different.

10. The method as claimed in claim 7, wherein the data stored in different physical pages of the first single-level cell block are scrambled according to different random seeds in the first set of random seeds, the data stored in different physical pages of the second single-level cell block are scrambled according to different random seeds in the second set of random seeds, and wherein the random seed utilized for scrambling the data of each physical page is stored in a spare region of the corresponding physical page.

11. The method as claimed in claim 10, wherein when reading the first data, the method further comprises:

reading the first data from the memory device;

decoding the first data; and

descrambling the decoded first data according to the corresponding random seed stored in the corresponding spare region.

12. The method as claimed in claim 10, further comprising:

reading the data that is stored in the first single-level cell block and writing the data directly into one of the multiple-level cell blocks;

reading the data that is stored in the second single-level cell block and writing the data directly into the multiple-level cell block; and

reading the data that is stored in the third single-level cell block and writing the data directly into the multiple-level cell block.