Refresh scheme in a memory controller
First Claim
1. A memory controller, comprising:
- a command queue for receiving and storing memory access requests for a memory;
an arbiter for selectively picking accesses from the command queue according to a first type of accesses and a second type of accesses, wherein the first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory;
a refresh logic circuit for generating a refresh command to a bank of the memory, and providing a priority indicator with the refresh command whose value is set according to a number of pending refreshes, wherein the refresh logic circuit assigns the priority indicator one of a first priority status and a second priority status; and
a final arbiter for selectively ordering the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator, wherein the final arbiter elevates the refresh command between the first type of accesses and the second type of accesses in response to the first priority status.
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Accused Products
Abstract
In one form, a memory controller includes a command queue, an arbiter, a refresh logic circuit, and a final arbiter. The command queue receives and stores memory access requests for a memory. The arbiter selectively picks accesses from the command queue according to a first type of accesses and a second type of accesses. The first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. The refresh logic circuit generates a refresh command to a bank of the memory and provides a priority indicator with the refresh command whose value is set according to a number of pending refreshes. The final arbiter selectively orders the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator.
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Citations
34 Claims
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1. A memory controller, comprising:
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a command queue for receiving and storing memory access requests for a memory; an arbiter for selectively picking accesses from the command queue according to a first type of accesses and a second type of accesses, wherein the first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory; a refresh logic circuit for generating a refresh command to a bank of the memory, and providing a priority indicator with the refresh command whose value is set according to a number of pending refreshes, wherein the refresh logic circuit assigns the priority indicator one of a first priority status and a second priority status; and a final arbiter for selectively ordering the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator, wherein the final arbiter elevates the refresh command between the first type of accesses and the second type of accesses in response to the first priority status. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A data processing system, comprising:
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a memory accessing agent for providing memory access requests for a memory; a memory system coupled to the memory accessing agent; and a memory controller coupled to the memory system and the memory accessing agent, the memory controller comprising; a command queue for storing memory access commands received from the memory accessing agent; an arbiter for selectively picking memory accesses from the command queue according to a first type of access and a second type of access, wherein each type of access corresponds to a different page status of a bank in the memory; and a final arbiter that arbitrates based on input received from a refresh logic circuit that generates a refresh command to the bank of the memory and provides a priority indicator with the refresh command, whose value is set according to a number of pending refreshes, to selectively order the refresh command with respect to a first type of access and a second type of access, wherein the memory controller assigns the priority indicator one of a first priority status and a second priority status, and elevates the refresh command between the first type of access and the second type of access in response to the first priority status. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method for managing refresh of a memory in a memory system via a memory controller, the method comprising:
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receiving a plurality of memory access requests; storing the plurality of memory access requests in a command queue; and selectively picking memory accesses requests from the command queue according to a first type of accesses and a second type of accesses that correspond to different page statuses of corresponding memory accesses in the memory; generating a refresh command to a bank of the memory, and providing a priority indicator with the refresh command whose value is set according to a number of pending refreshes, wherein providing the priority indicator to the refresh command further comprises assigning the priority indicator one of a first priority status and a second priority status, and elevating the refresh command between the first type accesses and the second type accesses in response to the first priority status; and selectively ordering the refresh command with respect to memory access requests of the first type of accesses and the second type of accesses based on the priority indicator. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification