Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations

• US 10,593,396 B2
• Filed: 09/05/2018
• Issued: 03/17/2020
• Est. Priority Date: 07/06/2018
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Tzoufras, Michail, Gajek, Marcin
• Primary Examiner(s): Hidalgo, Fernando
• Application Number:
  US16/122,773
• Publication Number:
  US 20200013456A1
• Time in Patent Office: 559 Days
• Field of Search: 365158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/5607 using magnetic storage elements
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

Claims

1. A memory device comprising:

an array of Multi-Bit Cells (MBCs), the MBCs each including a first and second cell element having different sets of state parameter values, wherein a pinned magnetization polarization of the first cell is opposite a pinned magnetization polarization of the second cell;

one or more memory circuits configured to;

sequentially apply a first set of state programming conditions and a second set of state programming conditions to a selected plurality of the MBCs, wherein the first cell element will be in a first state after programming with the first set of state programming conditions and the first cell element will be in a second state after programming with the second set of state programming conditions;

determine, after applying each of the set of programming conditions, a state change result for the selected plurality of the MBCs; and

determine a read state of the selected plurality of MBCs based on the determined state change results.

2. The memory device of claim 1, wherein the first cell element comprises a higher resistance element in relationship to the second cell element.

3. The memory device of claim 1, wherein the one or more memory circuits include:

a word line circuit, a bit line circuit and a source line circuit configured to bias the selected plurality of MBCs with a first set of sense voltage levels, and a sense circuit to sense a first instance of a sense level of the selected plurality of MBCs;

the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with a first set of program voltage levels to program the first cell element to a first state;

the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with the first set of sense voltage levels, and the sense circuit to sense a second instance of the sense level of the selected plurality of MBCs;

the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with a second set of sense voltage levels, and the sense circuit to sense a third instance of the sense level of the selected plurality of MBCs;

the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with a second set of program voltage levels to program the first cell element to a second state;

the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with the second set of sense voltage levels, and the sense circuit to sense a fourth instance of the sense level of the selected plurality of MBCs; and

a read logic circuit configured to determine the read state of the selected plurality of MBCs based on a presence or absence of a change between the first instance of the sense level and the second instance of the sense level and a presence or absence of a change between the third instance of the sense level and the fourth instance of the sense level.

4. The memory device of claim 3, wherein:

the first set of program voltage levels include a predetermined negative potential between bit lines and source lines of the selected plurality of MBCs; and

the second set of program voltage levels include a predetermined positive potential between bit lines and source lines of the selected plurality of MBCs.

5. The memory device of claim 3, wherein:

the first set of program voltage levels include a predetermined positive potential between bit lines and source lines of the selected plurality of MBCs; and

the second set of program voltage levels include a predetermined negative potential between bit lines and source lines of the selected plurality of MBCs.

6. The memory device of claim 3, wherein the read logic circuit includes:

a plurality of first switches and first capacitors coupled together and configured to store the first instance of the sense level of the selected plurality of MBCs;

a plurality of second switches and second capacitors coupled together and configured to store the second instance of the sense level and the third instance of the sense level of the selected plurality of MBCs;

a plurality of third switches and third capacitors coupled together and configured to store the fourth instance of the sense level of the selected plurality of MBCs;

a plurality of first comparators coupled to the plurality of first switches and first capacitors and the plurality of second switches and second capacitors and configured to compare the second instance of the sense level to the first instance of the sense level; and

a plurality of second comparators coupled to the plurality of second switches and second capacitors and the plurality of third switches and third capacitors and configured to compare the fourth instance of the sense level to the third instance of the sense level.

7. The memory device of claim 1, wherein the MBCs include a first Magnetic Tunnel Junction (MTJ) element and a second MTJ element.

8. The memory device of claim 1, wherein the one or more memory circuits are further configured to write the determined read state back to the MBCs.

9. A memory device comprising:

a Multi-Bit Cell (MBC) coupled between a bit line and a source line, wherein the MBC includes a first MTJ element, a second MTJ element and a selector coupled in series, wherein the first and second MTJ elements have different low-resistance levels and different high-resistance levels, and wherein the first and second MTJ elements have opposite pinned magnetization polarization orientations;

one or more memory circuits configured to;

sense a first sense voltage of the MBC;

program the MBC using a first program voltage after sensing the first sense voltage, wherein the first MTJ element will be in a known state after programming;

sense a second sense voltage of the MBC after programming the MBC using the first program voltage;

compare the second sense voltage to the first sense voltage, after sensing the second sense voltage, to determine a first resistance change state;

program the MBC using a second program voltage after sensing the second sense voltage, wherein the state of the first MTJ element will be flipped;

sense a third sense voltage of the MBC after programming the MBC using the second program voltage;

compare the third sense voltage to the second sense voltage, after sensing the third sense voltage, to determine a second resistance changed state; and

determine a read state of the MBC based on the first resistance change state and the second resistance change state.

10. The memory device of claim 9, wherein:

the first program voltage comprises a predetermined negative potential; and

the second program voltage comprises a predetermined positive potential.

11. The memory device of claim 9, wherein:

the first program voltage comprises a predetermined positive potential; and

the second program voltage comprises a predetermined negative potential.

12. The memory device of claim 9, wherein the one or more memory circuits includes:

a current or voltage source to apply a fixed current or fixed voltage to sense the MBC;

a first switch coupled to a first capacitor configured to store the first sense voltage of the MBC on the first capacitor;

a second switch coupled to a second capacitor configured to store the second sense voltage of the MBC on the second capacitor;

a third switch coupled to a third capacitor configured to store the third sense voltage of the MBC on the third capacitor;

a first comparator coupled to the first and second capacitors and configured to compare the second sense voltage to the first sense voltage; and

a second comparator coupled to the second and third capacitor and configured to compare the third sense voltage to the second sense voltage.

13. The memory device of claim 9, wherein the one or more memory circuits are further configured to;

write the determined read state back to the MBC.

14. A method comprising:

sensing a first instance of state parameter of a Multi-Bit Cell (MBC), wherein the MBC includes a first and a second cell element having different sets of state parameter values and having different pinned magnetization polarizations;

programming the MBC using a first set of state programming conditions after sensing the first state parameter value, wherein the first cell element will be in a first state after programming;

sensing a second instance of the state parameter of the MBC after programming the MBC using the first set of state programming conditions;

comparing the second instance of the state parameter to the first instance of the state parameter, to determine a first state change result;

programming the MBC using a second set of state programming conditions after sensing the second instance of the state parameter, wherein the first cell element will be in a second state after programming;

sensing a third instance of the state parameter of the MBC after programming the MBC using the second set of state programming conditions;

comparing the third instance of the state parameter to the second instance of the state parameter, to determine a second state change result; and

outputting a read state of the MBC based on the first state change result and the second state change result.

15. The method according to claim 14, wherein the MBC includes:

a first Magnetic Tunnel Junction (MTJ) element including a first resistive state and a second resistive state; and

a second MTJ element including a third resistive state and a fourth resistive state.

16. The method according to claim 15, wherein the first resistive state is greater than the third resistive state and the second resistive state is greater than the fourth resistive state.

17. The method according to claim 15, wherein:

sensing the first instance of the state parameter of the MBC comprises applying a set of sensing conditions and sensing a first sense voltage in response to the set of sensing conditions;

programming the MBC using a first set of state programming conditions comprises applying a first programming voltage to the MBC, wherein the first MTJ element will be in the first state after programming;

sensing a second instance of the state parameter of the MBC comprises applying the set of sensing conditions and sensing a second sense voltage in response to the set of sense conditions;

programming the MBC using a second set of state programming conditions comprises applying a second programming voltage to the MBC, wherein the first MTJ element will be in the second state after programming; and

sensing a third instance of the state parameter of the MBC comprises applying the set of sensing conditions and sensing a third sense voltage in response to the set of sense conditions.

18. The method according to claim 17, wherein:

the first programming voltage comprises a predetermined negative programming voltage; and

the second programming voltage comprises a predetermined positive programming voltage.

19. The method according to claim 17, wherein:

the first programming voltage comprises a predetermined positive programming voltage; and

the second programming voltage comprises a predetermined negative programming voltage.

20. A method of reading from an array of Multi-Bit Cells (MBCs) comprising:

receiving a read command for a selected plurality of MBCs in the army of MBCs, wherein the MBCs each include a first and second MTJ coupled in series and having opposite pinned magnetization polarizations;

sequentially applying a first and second switching condition to the selected plurality of MBCs, wherein a state of the first MTJ of each selected MBC flips after the second switching condition with respect to the state of the first MTJ after the first switching condition;

determining for each selected MBC, after applying each switching condition, whether a state of the MBCs have changed; and

determining for each selected MBC, a read state of the MBCs based on whether or not the state of the MBCs changed in response to each applied switching condition.

21. The method of claim 20, wherein:

the first switching condition comprises a negative programming voltage; and

the second switching condition comprises a positive programming voltage.

22. The method of claim 20, wherein:

the first switching condition comprises a positive programming voltage; and

the second switching condition comprises a negative programming voltage.

23. The method of claim 20, further comprising:

writing back the determined read state to the MBCs.

24. The method of claim 20, wherein the selected plurality of MBCs includes one of a computing device readable media word, a computing device readable media page, or a computing device readable media code word.