Array architecture for large scale integration of phase-change material (PCM) radio frequency (RF) switches

• US 10,593,404 B2
• Filed: 04/12/2019
• Issued: 03/17/2020
• Est. Priority Date: 08/14/2018
• Status: Active Grant

• Current Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Original Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Inventors: Slovin, Gregory P., El-Hinnawy, Nabil, Howard, David J.
• Primary Examiner(s): Seven, Evren
• Application Number:
  US16/383,453
• Publication Number:
  US 20200058354A1
• Time in Patent Office: 340 Days
• Field of Search: None
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2013/008 Write by generating heat in the surroundings of the memory material, e.g. thermowrite
• CPC Class Codes: G11C 2213/73 Array where access device function, e.g. diode function, being merged with memorizing function of memory element
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8613 Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

An array includes a shared pulse generator and a plurality of cells. A selected cell the plurality of cells includes a phase-change material (PCM) and a heating element, the heating element being transverse to the PCM. The array further includes a row selector configured to connect the shared pulse generator to the selected cell, and a selector configured to connect the selected cell to a ground. The shared pulse generator provides an electrical pulse to cause the heating element in the selected cell to generate a heat pulse. In one approach, the selected cell also includes a non-linear device such as a diode, and the shared pulse generator provides the electrical pulse to a PCM RF switch of the selected cell through the non-linear device to change a state of the PCM RF switch.

Claims

1. An array comprising:

a shared pulse generator;

a plurality of cells, a selected cell in said plurality of cells comprising;

a non-linear device;

a phase-change material (PCM) radio frequency (RF) switch;

a row selector configured to connect said shared pulse generator to said selected cell;

a column selector configured to connect said selected cell to a ground;

wherein said shared pulse generator provides an electrical pulse to said PCM RF switch of said selected cell through said non-linear device to change a state of said PCM RF switch.

2. The array of claim 1, wherein said non-linear device is connected to a heating element of said PCM RF switch.

3. The array of claim 1, wherein said non-linear device is selected from the group consisting of a diode, a diode-configured transistor, an ovonic threshold switching device, and a resistive memory element.

4. The array of claim 1, further comprising a row decoder configured to enable said row selector, and a column decoder configured to enable said column selector.

5. The array of claim 1, further comprising:

another row selector configured to connect another shared pulse generator to another selected cell in said plurality of cells;

said column selector further configured to connect said another selected cell to said ground.

6. The array of claim 5, further comprising a row decoder configured to concurrently enable said row selector and said another row selector.

7. The array of claim 1, wherein said electrical pulse causes a heating element of said PCM RF switch to generate a heat pulse.

8. The array of claim 7, wherein said heat pulse transforms an active segment of a PCM of said PCM RF switch, said active segment approximately defined by said heating element.

9. The array of claim 8, wherein said PCM is selected from the group consisting of germanium telluride (Ge_XTe_Y), germanium antimony telluride (Ge_XSb_YTe_Z), germanium selenide (Ge_XSe_Y), and any other chalcogenide.

10. The array of claim 1, wherein said row selector comprises a p-type field effect transistor (PFET).

11. An array comprising:

a shared pulse generator;

a plurality of cells, a selected cell in said plurality of cells comprising;

a phase-change material (PCM);

a heating element;

said heating element transverse to said PCM;

a row selector configured to connect said shared pulse generator to said selected cell;

a column selector configured to connect said selected cell to a ground;

wherein said shared pulse generator provides an electrical pulse to cause said heating element in said selected cell to generate a heat pulse;

wherein another row selector is configured to connect another shared pulse generator to another selected cell in said plurality of cells, and wherein said column selector further configured to connect said another selected cell to said ground.

12. The array of claim 11, further comprising a row decoder configured to concurrently enable said row selector and said another row selector.

13. The array of claim 11, wherein said row selector connects said shared pulse generator to a first terminal of said heating element, and said column selector connects a second terminal of said heating element to said ground.

14. The array of claim 11, further comprising a row decoder configured to enable said row selector, and a column decoder configured to enable said column selector.

15. The array of claim 11, wherein said heat pulse transforms an active segment of said PCM, said active segment approximately defined by said heating element.

16. The array of claim 11, further comprising PCM contacts connected to passive segments of said PCM.

17. The array of claim 11, wherein said PCM is selected from the group consisting of germanium telluride (Ge_XTe_Y), germanium antimony telluride (Ge_XSb_YTe_Z), germanium selenide (Ge_XSe_Y), and any other chalcogenide.

18. The array of claim 11, wherein said row selector comprises a p-type field effect transistor (PFET).

19. An array comprising:

a shared pulse generator;

a plurality of cells, a selected cell in said plurality of cells comprising;

a phase-change material (PCM);

a heating element;

said heating element transverse to said PCM;

a row selector configured to connect said shared pulse generator to said selected cell, wherein said row selector comprises an n-type field effect transistor (NFET), and said row selector is coupled to a level shifter;

a column selector configured to connect said selected cell to a ground;

wherein said shared pulse generator provides an electrical pulse to cause said heating element in said selected cell to generate a heat pulse.

20. The array of claim 19, wherein said PCM is selected from the group consisting of germanium telluride (Ge_XTe_Y), germanium antimony telluride (Ge_XSb_YTe_Z), germanium selenide (Ge_XSe_Y), and any other chalcogenide.