Chip capacitor, circuit assembly, and electronic device

• US 10,593,480 B2
• Filed: 07/10/2018
• Issued: 03/17/2020
• Est. Priority Date: 11/02/2012
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Yamamoto, Hiroki, Watanabe, Keishi, Tamagawa, Hiroshi
• Primary Examiner(s): Ngo, Ngan V
• Application Number:
  US16/031,212
• Publication Number:
  US 20180323011A1
• Time in Patent Office: 616 Days
• CPC Class Codes: H01G 2/06 specially adapted for mounting on a printed-circuit support
• CPC Class Codes: H01G 4/005 Electrodes
• CPC Class Codes: H01G 4/228 Terminals
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01G 4/40 Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/101 : including resistors or capacitors only
• CPC Class Codes: H01L 28/40 : Capacitors
• CPC Class Codes: H01L 29/66189 : with PN junction, e.g. hybrid capacitors
• CPC Class Codes: H01L 29/94 : Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 1/162 : incorporating printed capacitors
• CPC Class Codes: H05K 1/18 : Printed circuits structurally associated with non-printed electric components H05K1/0201, H05K1/023, H05K1/0243, and H05K1/16 take precedence
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 2201/10015 : Non-printed capacitor
• CPC Class Codes: H05K 2201/10045 : Mounted network component having plural terminals
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H10B 63/20 : comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

Claims

1. A chip capacitor, comprising:

a substrate having a longitudinal direction;

a first external electrode and a second external electrode formed on or over the substrate;

a capacitor element connected between the first external electrode and the second external electrode, the capacitor element extending in the longitudinal direction of the substrate; and

a diode connected between the first external electrode and the second external electrode, and in parallel to the capacitor element, the diode extending in the longitudinal direction of the substrate,

wherein the capacitor element includes

a lower electrode,

a capacitance film that is laminated on or over the lower electrode, and

an upper electrode facing the lower electrode across the capacitance film, and

wherein the upper electrode includes a trimming region capable of being fused, the trimming region having a line shape.

2. The chip capacitor according to claim 1, wherein a cathode of the diode is connected to the first external electrode.

3. The chip capacitor according to claim 1, wherein the first external electrode is a power-supply electrode.

4. The chip capacitor according to claim 1, wherein the diode includes a bidirectional diode.

5. The chip capacitor according to claim 1, wherein the substrate is a semiconductor substrate and the diode includes an impurity diffusion layer formed in the semiconductor substrate.

6. The chip capacitor according to claim 5, wherein the lower electrode includes an impurity diffusion layer formed inside the semiconductor substrate.

7. The chip capacitor according to claim 1, wherein the substrate is a semiconductor substrate,

the lower electrode includes an impurity diffusion layer formed inside the semiconductor substrate, and

the diode includes an impurity diffusion layer continuous to the impurity diffusion layer of the lower electrode.

8. The chip capacitor according to claim 1, wherein the diode includes a portion formed in a region directly below at least one of the first external electrode and the second external electrode.

9. The chip capacitor according to claim 1, wherein the entirety of the diode is formed in a region directly below at least one of the first external electrode and the second external electrode.

10. The chip capacitor according to claim 1, wherein the diode includes a polysilicon film formed on the substrate.

11. The chip capacitor according to claim 1, further comprising:

a first pad portion connected to the capacitor element; and

a second pad portion connected to the diode; and

wherein one of the first external electrode and the second external electrode is formed to extend across the first pad portion and the second pad portion to electrically connect the first pad portion and the second pad portion.

12. The chip capacitor according to claim 11, further comprising:

an insulating layer disposed between the first pad portion and the second pad portion and separating the first pad portion and the second pad portion; and

wherein the first external electrode or the second external electrode extends across the insulating layer to be joined to both the first pad portion and the second pad portion.

13. The chip capacitor according to claim 1, wherein each of the first external electrode and the second external electrode is formed to extend across a front surface and a side surface of the substrate and integrally has a front surface portion covering the front surface and a side surface portion covering the side surface.

14. The chip capacitor according to claim 1, wherein

the lower electrode is connected to one of the first external electrode and the second external electrode, and

the upper electrode is connected to the other of the first external electrode and the second external electrode.

15. The chip capacitor according to claim 1, wherein

the substrate has a plurality of trenches,

the lower electrode is formed on or over an inner surface of the plurality of trenches or inside the inner surface of the plurality of trenches,

the capacitance film is formed along the inner surface of the plurality of trenches, and

the upper electrode is embedded in the plurality of trenches via the capacitance film such that the upper electrode straddles the plurality of trenches and collectively covers the plurality of trenches.

16. The chip capacitor according to claim 15, wherein the trench has a side wall surface intersecting a major surface of the substrate, and the capacitance film is formed along the side wall surface of the trench.

17. The chip capacitor according to claim 16, wherein the upper electrode includes a polysilicon film.

18. The chip capacitor according to claim 15, wherein

the capacitor element includes a plurality of capacitor components, and

a plurality of the trimming regions disconnectably connect each of the plurality of the capacitor components to the first external electrode and the second external electrode.

22. The chip capacitor according to claim 1, further comprising:

a resistor element connected between the first external electrode and the second external electrode, and in parallel to the capacitor element.

23. A circuit assembly, comprising:

the chip capacitor according to claim 1; and

a mounting substrate having lands, soldered to the first external electrode and the second external electrode, on or over a mounting surface facing a front surface of the substrate.

24. The circuit assembly according to claim 23,

wherein each of the first external electrode and the second external electrode of the chip capacitor is formed to extend across a front surface and a side surface of the substrate and integrally has a front surface portion covering the front surface and a side surface portion covering the side surface, and

solder covers the front surface portion and the side surface portion of each of the first external electrode and the second external electrode.

25. An electronic device, comprising:

the circuit assembly according to claim 23; and

a casing that houses the circuit assembly.

19. A chip capacitor, comprising:

a substrate having a longitudinal direction;

a first external electrode and a second external electrode formed on or over the substrate;

a capacitor element connected between the first external electrode and the second external electrode, the capacitor element extending in the longitudinal direction of the substrate; and

a diode connected between the first external electrode and the second external electrode, and in parallel to the capacitor element, the diode extending in the longitudinal direction of the substrate,

wherein the capacitor element includes;

a lower electrode,

a capacitance film that is laminated on or over the lower electrode, and

an upper electrode facing the lower electrode across the capacitance film,

wherein the upper electrode includes a trimming region capable of being fused, the trimming region having a line shape.

20. The chip capacitor according to claim 19, wherein

the capacitor element includes a plurality of capacitor components connected in parallel between the first external electrode and the second external electrode, and

the plurality of capacitor components include:

a basic capacitance element, and

a plurality of adjusting capacitance elements respectively connected to the first external electrode and the second external electrode via a plurality of the trimming regions.

21. The chip capacitor according to claim 20, wherein the plurality of adjusting capacitance elements have mutually parallel strip shapes, have one ends thereof aligned at a side of one of the first external electrode and the second external electrode, and are lined up in order of length, and

the basic capacitance element includes a connection portion, disposed adjacent to an adjusting capacitance element of shortest length among the plurality of adjusting capacitance elements and connected to the one external electrode, and a main portion, formed integral to the connection portion and so as to avoid the plurality of adjusting capacitance elements and widening as the other of the first external electrode and the second external electrode is approached.