Semiconductor structures

• US 10,593,595 B2
• Filed: 08/31/2018
• Issued: 03/17/2020
• Est. Priority Date: 08/09/2016
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: Zhou, Fei
• Primary Examiner(s): Dinke, Bitew A
• Application Number:
  US16/119,369
• Publication Number:
  US 20180374752A1
• Time in Patent Office: 564 Days
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

Semiconductor structure is provided. An exemplary semiconductor structure includes a semiconductor substrate including fin structures. The fin structures include a plurality of first fin structures having a first width and a plurality of second fin structures. The second fin structure has a second width at a lower portion and a third width at an upper portion, and the second width is greater than each of the first width and the third width. The semiconductor structure includes a first isolation film formed on the semiconductor substrate and between adjacent fin structures. The first isolation film has a top surface lower than the fin structures. The upper portion of each second fin structure having the third width passes through the top surface of the first isolation film.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate including fin structures, the fin structures including a plurality of first fin structures having a first width and a plurality of second fin structures, wherein;

the second fin structure has a second width at a lower portion and a third width at an upper portion, and

the second width is greater than each of the first width and the third width; and

a first isolation film formed on the semiconductor substrate and between adjacent fin structures, wherein;

the first isolation film has a top surface lower than the fin structures, and

the upper portion of each second fin structure having the third width passes through the top surface of the first isolation film; and

a by-product layer formed on a top surface of the lower portion of the second fin structures, wherein the by-product layer has a top surface coplanar with the top surface of the first isolation film and a side surface coplanar with a side surface of the lower portion of the second fin structures.

2. The semiconductor structure according to claim 1, wherein:

the by-product layer has the second width and on a sidewall of the upper portion of the second fin structures having the third width.

3. The semiconductor structure according to claim 1, wherein:

the by-product layer is an oxidized layer.

4. The semiconductor structure according to claim 2, further including:

a second isolation film on a top portion of the first isolation film, on a sidewall of the by-product layer, and having a top surface coplanar with the first isolation film.

5. The semiconductor structure according to claim 4, wherein:

the second isolation film is formed on both sides of each second fin structure along a length direction of the second fin structure.

6. The semiconductor structure according to claim 1, wherein:

the first fin structures and the second fin structures are made of Si, Ge, or SiGe.

7. The semiconductor structure according to claim 1, wherein:

the upper portion of each second fin structure having the third width has a height portion in the first isolation film.

8. A semiconductor structure, comprising:

a semiconductor substrate including fin structures, the fin structures including a plurality of first fin structures having a first width and a plurality of second fin structures, wherein;

the second fin structure has a second width at a lower portion and a third width at an upper portion, and

the second width is greater than each of the first width and the third width;

a first isolation film formed on the semiconductor substrate and between adjacent fin structures, wherein;

the first isolation film has a top surface lower than the fin structures, and

the upper portion of each second fin structure having the third width passes through the top surface of the first isolation film;

a by-product layer formed on a top surface of the lower portion of the second fin structures having the second width and on a sidewall of the upper portion of the second fin structures having the third width;

a second isolation film on a top portion of the first isolation film, on a sidewall of the by-product layer, and having a top surface coplanar with the first isolation film; and

a control layer between the first and second isolation films and, between the second isolation film and the by-product layer.

9. The semiconductor structure according to claim 8, wherein a thickness of the control layer along a direction perpendicular to the sidewall surfaces of the second fin structures is in a range of approximately 5 Å

to 50 Å

.

10. The semiconductor structure according to claim 8, wherein the control layer is made of SiO_x, SiN_x, SiON, or a combination thereof.