Molded die last chip combination

• US 10,593,628 B2
• Filed: 04/24/2018
• Issued: 03/17/2020
• Est. Priority Date: 04/24/2018
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Bhagavat, Milind S., Agarwal, Rahul
• Primary Examiner(s): Tran, Minh Loan
• Application Number:
  US15/961,222
• Publication Number:
  US 20190326221A1
• Time in Patent Office: 693 Days
• Field of Search: None
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/485 Adaptation of interconnections, e.g. engineering charges, repair techniques
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/49844 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/52 : Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/538 : the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5382 : Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

Claims

1. A method of manufacturing a semiconductor chip device, comprising:

fabricating a redistribution layer (RDL) structure having multiple dielectric layers and a first external side and a second external side opposite to the first external side;

mounting an interconnect chip on the first external side of the RDL structure; and

mounting a first semiconductor chip and a second semiconductor chip on the second external side of the RDL structure after mounting the interconnect chip, the RDL structure and the interconnect chip electrically connecting the first semiconductor chip to the second semiconductor chip.

2. The method of claim 1, comprising at least partially encasing the interconnect chip in a first molding layer and fabricating the RDL structure on the first molding layer.

3. The method of claim 2, comprising at least partially encasing the first semiconductor chip and the second semiconductor chip in a second molding layer on the RDL structure.

4. The method of claim 1, wherein the RDL structure includes a first plurality of interconnects to connect to a circuit board when the semiconductor chip device is mounted on the circuit board.

5. The method of claim 1, wherein the first semiconductor chip includes a first PHY region connected to the interconnect chip and the second semiconductor chip includes a second PHY region connected to the interconnect chip.

6. The method of claim 1, comprising mounting the RDL structure, the interconnect chip and the first semiconductor chip and second semiconductor chip on a circuit board.

7. The method of claim 1, wherein the first semiconductor chip comprises a processor and the second semiconductor chip comprises a memory chip.

8. A method of interconnecting a first semiconductor chip to a second semiconductor chip, comprising:

at least partially encasing an interconnect chip in a first molding layer;

fabricating a redistribution layer (RDL) structure on the first molding layer;

mounting a first semiconductor chip and a second semiconductor chip on the RDL structure after the RDL structure is fabricated; and

interconnecting a first PHY region of the first semiconductor chip to a second PHY region of the second semiconductor chip with the interconnect chip and the RDL structure.

9. The method of claim 8, comprising at least partially encasing the first semiconductor chip and the second semiconductor chip in a second molding layer on the RDL structure.

10. The method of claim 8, wherein the RDL structure includes a first plurality of interconnects to connect to a circuit board when the first semiconductor chip and the second semiconductor chip are mounted on the circuit board.

11. The method of claim 10, comprising mounting the RDL structure, the interconnect chip and the first semiconductor chip and second semiconductor chip on the circuit board.

12. The method of claim 8, wherein the first semiconductor chip includes a first non-PHY region connected to the RDL structure and the second semiconductor chip includes a second non-PHY region connected to the RDL structure.

13. The method of claim 8, wherein the first semiconductor chip comprises a processor and the second semiconductor chip comprises a memory chip.

14. A semiconductor chip device, comprising:

a first molding layer;

an interconnect chip at least partially encased in the first molding layer;

a redistribution layer (RDL) structure positioned on the first molding layer and having at least one dielectric layer, plural conductor structures and a first side and a second side opposite to the first side;

a first semiconductor chip and a second semiconductor chip positioned on the second side of the RDL structure, the RDL structure and the interconnect chip electrically connecting the first semiconductor chip to the second semiconductor chip; and

a second molding layer at least partially encasing the first semiconductor chip and the second semiconductor chip.

15. The semiconductor chip device of claim 14, wherein the first molding layer includes a first plurality of interconnects to connect to a circuit board when the semiconductor chip device is mounted on the circuit board.

16. The semiconductor chip device of claim 15, comprising the circuit board, the semiconductor chip device being mounted on the circuit board.

17. The semiconductor chip device of claim 15, wherein conductor structures of the RDL structure have smaller gauge than the interconnects of the first molding layer.

18. The semiconductor chip device of claim 14, wherein the first semiconductor chip includes a first PHY region connected to the interconnect chip and the second semiconductor chip includes a second PHY region connected to the interconnect chip.

19. The semiconductor chip device of claim 18, wherein the first semiconductor chip includes a first non-PHY region connected to the RDL structure and the second semiconductor chip includes a second non-PHY region connected to the RDL structure.

20. The semiconductor chip device of claim 14, wherein the first semiconductor chip comprises a processor and the second semiconductor chip comprises a memory chip.