Warping reduction in silicon wafers

• US 10,593,631 B2
• Filed: 04/04/2018
• Issued: 03/17/2020
• Est. Priority Date: 04/04/2018
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Ranaweera, Jeewika
• Primary Examiner(s): Miller, Jami Valentine
• Application Number:
  US15/945,665
• Publication Number:
  US 20190311995A1
• Time in Patent Office: 713 Days
• Field of Search: 257 48
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence

Abstract

Techniques for reducing stress in an integrated circuit wafer are disclosed. A silicon substrate may include multiple integrated circuit chips and multiple scribe regions situated between the one of the multiple integrated circuit chips. A particular scribe region includes a plurality of layers and a stress reduction structure that includes, at a particular layer of the plurality of layers, a material whose coefficient of thermal expansion of materials is greater than a coefficient of thermal expansion of the silicon wafer.

Claims

1. An integrated circuit wafer, comprising:

a silicon substrate that includes;

a plurality of integrated circuit chips; and

a plurality of scribe regions situated between ones of the plurality of integrated circuit chips, wherein a particular scribe region of the plurality of scribe regions has a total area and includes a plurality of vertically stacked layers, wherein the particular scribe region includes a stress reduction structure located on at least a particular layer of the plurality of vertically stacked layers, wherein the stress reduction structure includes, on the particular layer, a material, wherein a collective area of the material on the particular layer is at least 40 percent of the total area of the particular scribe region, and wherein the material is metal that is electrically isolated from one or more metal regions included in the plurality of integrated circuit chips adjacent to the particular scribe region, and has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the silicon substrate.

2. The integrated circuit wafer of claim 1, wherein the metal is arranged in a plurality of non-contiguous regions.

3. The integrated circuit wafer of claim 2, wherein a space between a first and second of the non-contiguous regions corresponds to a minimum spacing specification for a semiconductor manufacturing process used to fabricate the plurality of integrated circuit chips.

4. The integrated circuit wafer of claim 1, wherein the stress reduction structure further includes, on a different layer of the plurality of vertically stacked layers, the material, wherein a collective area of the material on the different layer is at least 40 percent of the total area of the particular scribe region.

5. The integrated circuit wafer of claim 4, wherein the stress reduction structure further includes at least one via coupled to the material on the particular layer and the material on the different layer.

6. An apparatus, comprising:

a silicon substrate that includes;

a plurality of integrated circuit chips; and

a plurality of scribe regions situated between one of the plurality of integrated circuit chips, wherein a particular scribe region of the plurality of scribe regions includes;

a plurality of vertically stacked layers;

a stress reduction structure located on at least a particular layer of the plurality of vertically stacked layers, wherein the stress reduction structure includes, on the particular layer, a material, wherein a collective area of the material on the particular layer is at least 40 percent of a total area of the particular scribe region, and wherein the material is metal that is electrically isolated from one or more metal regions included in the plurality of integrated circuit chips adjacent to the particular scribe region, and has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the silicon substrate;

a test circuit; and

one or more mask alignment targets.

7. The apparatus of claim 6, wherein the metal within the particular layer is arranged in a plurality of non-contiguous regions.

8. The apparatus of claim 7, wherein a space between a first and second of the non-contiguous regions corresponds to a minimum spacing specification for a semiconductor manufacturing process used to fabricate the plurality of integrated circuit chips.

9. The apparatus of claim 6, wherein the stress reduction structure further includes on a different layer of the plurality of vertically stacked layers, the material, wherein a collective area of the material at the different layer is at least 40 percent of the total area of the particular scribe region.

10. The apparatus of claim 9, wherein the stress reduction structure further includes at least one via coupled to the material on the particular layer and the material on the different layer.

11. The apparatus of claim 6, wherein the material comprises copper.