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Method of maintaining the state of semiconductor memory having electrically floating body transistor

  • US 10,593,675 B2
  • Filed: 09/17/2019
  • Issued: 03/17/2020
  • Est. Priority Date: 03/02/2010
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • an array of semiconductor memory cells, the array comprising;

    a plurality of said semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include;

    a first bipolar device having a first floating base region, a first collector, and a first emitter, anda second bipolar device having a second floating base region, a second collector, and a second emitter,wherein said first floating base region is common to said second floating base region;

    wherein said first collector is common to said second collector;

    wherein a state of each of said at least two of said memory cells is maintained through a back-bias applied to said first and second collectors, andwherein said first and second collectors are commonly connected to said at least two of said memory cells;

    a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors; and

    a control circuit configured to apply said back-bias to said first and second collectors.

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