Logic circuit and semiconductor device

• US 10,593,710 B2
• Filed: 06/14/2018
• Issued: 03/17/2020
• Est. Priority Date: 10/16/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Tsubuku, Masashi, Noda, Kosei
• Primary Examiner(s): White, Dylan C
• Application Number:
  US16/008,437
• Publication Number:
  US 20180301476A1
• Time in Patent Office: 642 Days
• Field of Search: 257 71
• CPC Class Codes: G09G 2300/0439 Pixel structures
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 17/161 : in field-effect transistor switches
• CPC Class Codes: H03K 19/00315 : in field-effect transistor circuits
• CPC Class Codes: H03K 19/096 : Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence

Abstract

To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10⁻¹³ A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

Claims

1. A method for manufacturing a semiconductor device comprising:

the semiconductor device comprising;

a scan line driver circuit comprising a transistor; and

a pixel portion electrically connected to the scan line driver circuit,

the transistor comprising;

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and

an oxide insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer,

wherein the oxide insulating layer is in contact with the oxide semiconductor layer between the source electrode layer and the drain electrode layer,

wherein the oxide semiconductor layer comprises a crystal, and

wherein the oxide semiconductor layer comprises In, Ga, and Zn,

the method comprising;

performing a first heat treatment on the oxide semiconductor layer to reduce a hydrogen concentration of the oxide semiconductor layer;

forming the source electrode layer and the drain electrode layer after performing the first heat treatment;

forming the oxide insulating layer after forming the source electrode layer and the drain electrode layer; and

performing a second heat treatment to supply oxygen to the oxide semiconductor layer after forming the oxide insulating layer.

2. The method for manufacturing a semiconductor device according to claim 1,

wherein an off current per micrometer in a channel width of the transistor is less than or equal to 1×

10<sup>−

13</sup> A when a source-drain voltage Vd is 10 V and a source-gate voltage Vg is −

5 V.

3. The method for manufacturing a semiconductor device according to claim 1,

wherein an off current per micrometer in a channel width of the transistor is less than or equal to 1×

10<sup>−

17</sup> A when a source-drain voltage Vd is 10 V and a source-gate voltage Vg is −

5 V.

4. The method for manufacturing a semiconductor device according to claim 1,

wherein the oxide insulating layer is a silicon oxide layer.