Semiconductor device and method of manufacturing the same

• US 10,593,794 B2
• Filed: 12/05/2018
• Issued: 03/17/2020
• Est. Priority Date: 08/24/2011
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Omori, Kengo
• Primary Examiner(s): Chaudhari, Chandra
• Application Number:
  US16/210,247
• Publication Number:
  US 20190109231A1
• Time in Patent Office: 468 Days
• Field of Search: None
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.

Claims

1. A wide band gap semiconductor device comprising:

a semiconductor layer having a first surface and a second surface;

a trench formed on the first surface of the semiconductor layer;

a first region of a first conductivity type formed at a first surface of the semiconductor layer, the first region forming part of a side surface of the trench;

a second region of a second conductivity type formed on a side of the first region facing the second surface of the semiconductor layer, the second region forming part of the side surface of the trench;

a third region of the first conductivity type formed on a side of the second region facing the second surface of the semiconductor layer, the third region forming a bottom surface of the trench;

an insulating film formed on an inner surface of the trench; and

a first electrode embedded inside the insulating film in the trench, wherein

the second region integrally includes a first portion arranged closer to the first surface of the first surface of the semiconductor layer than to the bottom surface of the trench, and a second portion projecting from the first portion toward the second surface of the semiconductor layer to a depth below the bottom surface of the trench, and

the second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.

2. The wide band gap semiconductor device according to claim 1, further comprising a surrounded portion at least partially surrounded by the semiconductor layer, a bottom of the surrounded portion being between the first surface of the semiconductor layer and the second surface of the semiconductor layer, the surrounded portion being disposed immediately above the first portion of the second region.

3. The wide band gap semiconductor device according to claim 2, wherein an insulating layer is formed over the trench.

4. The wide band gap semiconductor device according to claim 3, wherein a source electrode is formed over the insulating layer and the semiconductor layer.

5. The wide band gap semiconductor device according to claim 4, wherein a highly doped impurity concentration region is formed beneath the surrounded portion.

6. The wide band gap semiconductor device according to claim 5, wherein

the semiconductor layer includes an SiC layer.

7. The wide band gap semiconductor device according to claim 6, wherein the surrounded portion includes a third portion of a conductive material.

8. The wide band gap semiconductor device according to claim 7, wherein the second portion of the second region has a width wider than a largest width of the surrounded portion.

9. The wide band gap semiconductor device according to claim 7, wherein an impurity concentration of the second portion is not more than 1/100 of an impurity concentration of the third portion.

10. The wide band gap semiconductor device according to claim 7, wherein

the second portion of the second region includes a peak immediately under the third portion formed along a position under a central portion in the width direction of the bottom surface of the surrounded portion.

11. The wide band gap semiconductor device according to claim 7, wherein

the second portion of the second region includes a peak immediately under the third portion, the peak formed along a position under an end portion in the width direction of the bottom surface of the surrounded portion.

12. The wide band gap semiconductor device according to claim 7, wherein

the second portion of the second region includes a plurality of peaks formed in parallel with one another at positions under both end portions, in a width direction, of the bottom surface of the surrounded portion.

13. The wide band gap semiconductor device according to claim 7, wherein the second portion projects in the form of a parabola such that an apex of the parabola is under a central portion, in a width direction, of the bottom surface of the surrounded portion.

14. The wide band gap semiconductor device according to claim 7, wherein the second portion projects in the form of two parabolas such that apexes of the two parabolas are located under a first and a second end portion, respectively, in the width direction, of the bottom surface of the surrounded portion.

15. The wide band gap semiconductor device according to claim 7, wherein respective peaks of the second portion of the second region are arranged in parallel with each other along the surrounded portion.

16. The wide band gap semiconductor device according to claim 7, wherein the second portion of the second region includes a plurality of peaks that are line-symmetrical with respect to a symmetry axis formed by a perpendicular plane passing through a central portion in a width direction of the bottom surface of the surrounded portion.

17. The wide band gap semiconductor device according to claim 7, wherein

the Si semiconductor layer includes an Si substrate and an Si epitaxial layer formed on the Si substrate, the Si epitaxial layer having a impurity concentration lower than an impurity concentration of the Si substrate, and

a peak of the second portion is not in contact with the Si substrate.

18. The wide band gap semiconductor device according to claim 7, wherein the thickness of the first portion is 0.5 μ

m to 0.9 μ

m and the thickness up to a peak of the second portion is 1.0 μ

m to 1.6 μ

m.

19. The wide band gap semiconductor device according to claim 7, wherein the trench projects 0.2 μ

m to 0.1 μ

m from an interface between the first portion and the third region.

20. The wide band gap semiconductor device according to claim 7, wherein the surrounded portion has a stripe shape, and

the second portion is formed in a stripe shape along the stripe-shaped surrounded portion.

21. The wide band gap semiconductor device according to claim 7, wherein the surrounded portion is shallower than the trench.

22. The wide band gap semiconductor device according to claim 7, the insulating film includes silicon oxide film.

23. The wide band gap semiconductor device according to claim 7, wherein the third region is partly arranged between the side surface of the trench and the boundary surface of the second portion of the second region.

24. The wide band gap semiconductor device according to claim 7, wherein an impurity concentration of part of the first portion is 1×

10¹⁷ to 5×

10¹⁷ cm<sup>−

3</sup>.