Automatic gain control (AGC) circuit, despreading circuit, and method for reproducing reception data

• US 10,594,282 B2
• Filed: 01/26/2018
• Issued: 03/17/2020
• Est. Priority Date: 01/27/2017
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: Hafuka, Takamitsu
• Primary Examiner(s): Tadese, Berhanu
• Application Number:
  US15/881,696
• Publication Number:
  US 20180219520A1
• Time in Patent Office: 781 Days
• Field of Search: None
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3078 Circuits generating control signals for digitally modulated signals
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 1/69 Spread spectrum techniques
• CPC Class Codes: H04B 1/7073 Synchronisation aspects

Abstract

An automatic gain control circuit controls a gain of a wireless receiver in accordance with an amplitude of a reception signal. The automatic gain control circuit includes a reference level calculator, a register, a reference level adjuster, and a bit width conversion circuit. The reference level calculator calculates a reference level on the basis of the amplitude of the reception signal. The register stores an adjustment value. The reference level adjuster adjusts the reference level on the basis of the adjustment value stored in the register. The bit width conversion circuit performs a bit width conversion for the entire amplitude direction by changing a bit pitch for determining discrete data values of the reception signal, on the basis of the adjusted reference level.

Claims

1. An automatic gain control circuit for controlling a gain:

of a wireless receiver in accordance with an amplitude of a reception signal, the automatic gain control circuit comprising;

a reference level calculator configured to calculate a reference level of bit width conversion based on an amplitude of the reception signal;

a register configured to store an adjustment value;

a reference level adjuster configured to adjust said reference level calculated by said reference level calculator based on the adjustment value stored in the register to generate an adjusted reference level; and

a bit width conversion circuit configured to perform a bit width conversion by dividing the amplitude of the reception signal, and changing borders for the dividing of the amplitude of the reception signal in accordance with the adjustment of the reference level performed by the reference level adjuster.

2. The automatic gain control circuit according to claim 1, further comprising:

a synchronous signal reception terminal configured to receive a synchronous signal of the reception signal; and

a selector, wherein

the register stores a plurality of adjustment values for the reference level, and the selector selects one of the adjustment values from the register in accordance with the synchronous signal, and the reference level adjuster generates the adjusted reference level based on the one of the adjustment values.

3. The automatic gain control circuit according to claim 1, wherein the reference level adjuster subtracts the adjustment value from the reference level to generate the adjusted reference level.

4. The automatic gain control circuit according to claim 2, wherein

the reference level adjuster has a subtractor configured to subtract the adjustment value from the reference level to generate the adjusted reference level, and

in an asynchronous state to the reception signal, a first adjustment value is selected from the register and supplied to the subtractor, and in response to the synchronous signal, a second adjustment value greater than the first adjustment value is selected from the register and supplied to the subtractor.

5. A de-spreading circuit comprising:

an automatic gain control circuit comprising;

a reference level calculator configured to calculate a reference level of bit width conversion based on an amplitude of a reception signal;

a register configured to store an adjustment value;

a reference level adjuster configured to adjust said reference level calculated by said reference level calculator based on the adjustment value stored in the register to generate an adjusted reference level lower than the reference level;

a bit width conversion circuit configured to perform a bit width conversion by dividing the amplitude of the reception signal and changing borders for the dividing of the amplitude of the reception signal in accordance with the adjustment of the reference level performed by the reference level adjuster;

a correlator configured to generate a correlation value signal representing a correlation value between a bit width converted signal whose bit width has been converted by the bit width conversion circuit and a spreading sequence;

a comparison circuit configured to perform a comparison between the correlation value and a threshold value, to generate a comparison signal representing a comparison result;

a synchronization control circuit configured to generate a synchronous signal based on the comparison signal; and

a symbol timing generation circuit configured to generate a symbol timing signal representing a symbol timing and a reception clock based on the synchronous signal and the comparison signal; and

a data reproduction circuit configured to generate reception data based on the correlation value signal and the symbol timing signal.

6. The despreading circuit according to claim 5, wherein the register stores a plurality of adjustment values for the reference level, and selects one of the plurality of adjustment values from the register in accordance with the synchronous signal from the synchronization control circuit.

7. A method for reproducing reception data comprising:

calculating a reference eve of bit width conversion based on an amplitude of a reception signal;

holding a plurality of adjustment values for the calculated reference level;

receiving a synchronous signal of the reception signal;

in an asynchronous state to the reception signal, selecting a first adjustment value from the adjustment values, and generating an adjusted reference level by subtracting the first adjustment value from the calculated reference level;

in a synchronous state to the reception signal in response to the synchronous signal, selecting a second adjustment value greater than the first adjustment value from the adjustment values, and

generating an adjusted reference level by subtracting the second adjustment value from the calculated reference level;

performing a bit width conversion by dividing the amplitude of the reception signal, and changing borders for the dividing of the amplitude of the reception signal in accordance with the adjustment of the reference level, to generate a bit width converted signal;

generating a correlation value signal representing a correlation value between the bit width converted signal and a spreading sequence;

making a comparison between the correlation value and a threshold value, to generate a comparison signal representing a comparison result;

generating a synchronous signal based on the comparison signal;

generating a symbol timing signal representing a symbol timing and a reception clock based on the synchronous and the comparison signal; and

generating the reception data based on the correlation value signal and the symbol timing signal.

8. An automatic gain control circuit for controlling a gain of a wireless receiver in accordance with an amplitude of a reception signal, the automatic gain control circuit comprising:

a reference level calculator configured to calculate a reference level of bit width conversion based on a summation signal which is obtained by summing up a square of an amplitude of an in-phase signal of reception signal and the square of an amplitude, of a quadrature signal of the reception signal;

a register configured to store an adjustment value;

a reference level adjuster configured to adjust said reference level calculated by said reference level calculator based on the adjustment value stored in the register to generate an adjusted reference level; and

a bit width conversion circuit configured to perform a bit width conversion by dividing the amplitude of the reception signal in accordance with said reference level adjusted by the reference level adjuster.