Programmable structured arrays

• US 10,594,320 B2
• Filed: 01/22/2018
• Issued: 03/17/2020
• Est. Priority Date: 12/04/2003
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Le, Don P
• Application Number:
  US15/877,224
• Publication Number:
  US 20180159537A1
• Time in Patent Office: 785 Days
• Field of Search: 326 38, 326 41
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

Claims

1. A programmable switch matrix, comprising:

a matrix of wires including a first plurality of non-crossing wires and a second plurality of non-crossing wires, wherein the first plurality of non-crossing wires intersect the second plurality of non-crossing wires at a plurality of intersection points; and

a plurality of programmable switches comprising a programmable switch at each intersection point of the plurality of intersection points, wherein each programmable switch includes;

a pass-gate coupled between a first wire of the first plurality of non-crossing wires and a second wire of the second plurality of non-crossing wires, wherein the programmable switches are on a layer of the programmable switch matrix that is different from a layer on which the first wire is located and different from a layer on which the second wire is located; and

a configuration circuit coupled to the pass-gate, wherein the pass-gate is configured to electrically connect the first wire and the second wire in response to an output of the configuration circuit having a first state and to electrically disconnect the first wire and the second wire in response to the output of the configuration circuit having a second state.

2. The programmable switch matrix of claim 1, wherein the pass-gate and the configuration circuit comprise thin film transistors (TFTs).

3. The programmable switch matrix of claim 1, wherein the first wire and the second wire are both located on a layer on one side of the layer comprising the programmable switches.

4. The programmable switch matrix of claim 1, wherein the first wire and the second wire are located on respective layers on opposite sides of the layer comprising the programmable switches.

5. The programmable switch matrix of claim 1, wherein the configuration circuit comprises a memory element, and wherein the output comprises a control signal that has a first voltage level if the memory element has a first polarity and a second voltage level if the memory element has a second polarity.

6. The programmable switch matrix of claim 1, wherein the configuration circuit comprises:

a first anti-fuse, wherein if the first anti-fuse is blown, a logic high signal is applied to the pass-gate to cause the pass-gate to electrically connect the first wire and the second wire; and

a second anti-fuse, wherein if the second anti-fuse is blown, a logic low signal is applied to the pass-gate to cause the pass-gate to electrically disconnect the first wire and the second wire.

7. The programmable switch matrix of claim 1, wherein the configuration circuit comprises a floating gate, a transistor, a diode, and a capacitor that couples the floating gate to a control gate;

wherein the configuration circuit is configured such that a voltage applied to the control gate is coupled to the floating gate through the capacitor and generates a signal to cause the pass-gate to electrically connect the first wire and the second wire, and wherein the configuration circuit is further configured such that a voltage applied to the transistor causes charge to be removed from the floating gate through the diode to cause the pass-gate to electrically disconnect the first wire and the second wire.

8. The programmable switch matrix of claim 7, wherein the configuration circuit further comprises another capacitor coupled between the floating gate and the pass-gate.

9. The programmable switch matrix of claim 1, wherein the configuration circuit comprises a type of memory circuit selected from the group comprising:

fuse, anti-fuse, EPROM, EEPROM, flash, ferro-electric, magnetic, SRAM, DRAM, metal optional, optical, laser fuse, photo-electric, electro-chemical, electrolytic, carbon nanotube, electro-mechanical, electro-magnetic, and resistance modulating.

10. The programmable switch matrix of claim 1, wherein the first plurality of non-crossing wires and the second plurality of non-crossing wires are configured to be electrically interconnected in a pattern according to the output of the configuration circuit of the programmable switch at each intersection point of the plurality of intersection points.

11. The programmable switch matrix of claim 10, wherein the pattern is changeable in response to a change in the output of a configuration circuit of a programmable switch at one or more intersection points of the plurality of intersection points.

12. A method of fabricating a programmable switch matrix, the method comprising:

forming a matrix of wires comprising a first plurality of non-crossing wires and a second plurality of non-crossing wires, wherein the first plurality of non-crossing wires intersect the second plurality of non-crossing wires at a plurality of intersection points; and

forming a programmable switch at each intersection point of the plurality of intersection points, wherein said forming a programmable switch comprises;

forming a pass-gate coupled between a first wire of the first plurality of non-crossing wires and a second wire of the second plurality of non-crossing wires, wherein the pass-gate is on a layer of the programmable switch matrix that is different from a layer on which the first wire is located and different from a layer on which the second wire is located; and

forming a configuration circuit coupled to the pass-gate, wherein the pass-gate is configured to electrically connect the first wire and the second wire in response to an output of the configuration circuit having a first state and to electrically disconnect the first wire and the second wire in response to the output of the configuration circuit having a second state.

13. The method of claim 12, wherein said forming a matrix of wires comprises forming the first wire and the second wire on a layer on one side of the layer comprising the pass-gate.

14. The method of claim 12, wherein said forming a matrix of wires comprises forming the first wire and the second wire on respective layers on opposite sides of the layer comprising the pass-gate.

15. The method of claim 12, wherein the pass-gate and the configuration circuit comprise thin film transistors (TFTs).

16. A method of fabricating a programmable switch matrix, the method comprising:

forming a first layer including first metal wires;

forming a second layer including second metal wires;

forming a third layer including an array of pass-gates, wherein the third layer is different from the first layer and different from the second layer;

coupling the array of pass-gates and the first metal wires through a first plurality of via connections; and

coupling the array of pass-gates to the second metal wires through a second plurality of via connections, wherein the array of pass-gates is operable to configure different combinations of connections between the first and second metal wires by turning on a corresponding combination of the pass-gates, and wherein the different combinations of connections comprise a connection between;

at least two of only the first metal wires;

at least two of only the second metal wires; and

one of the first metal wires and one of the second metal wires.

17. The method of claim 16, further comprising forming, in the third layer, a configuration circuit coupled to the array of pass-gates, wherein the array of pass-gates are configured to be turned on and to be turned off under control of the configuration circuit.

18. The method of claim 17, wherein said forming a configuration circuit comprises forming a plurality of memory elements coupled to the array of pass-gates, wherein a first subset of the pass-gates is configured to be turned on and a second subset of the pass-gates is configured to be turned off according to bit values stored in the memory elements.

19. The method of claim 17, wherein said forming a configuration circuit comprises:

forming a first anti-fuse, wherein if the first anti-fuse is blown, a logic high signal is applied to a respective pass-gate to turn on the pass-gate; and

forming a second anti-fuse, wherein if the second anti-fuse is blown, a logic low signal is applied to a respective pass-gate to turn off the pass-gate.

20. The method of claim 17, wherein said forming a configuration circuit comprises forming a floating gate, a transistor, a diode, and a capacitor that couples the floating gate to a control gate;

wherein the configuration circuit is configured such that a voltage applied to the control gate is coupled to the floating gate through the capacitor and generates a signal to turn on a respective pass-gate, and wherein the configuration circuit is further configured such that a voltage applied to the transistor causes charge to be removed from the floating gate through the diode and turns off a respective pass-gate.