Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells

• US 10,594,322 B2
• Filed: 08/13/2019
• Issued: 03/17/2020
• Est. Priority Date: 07/11/2017
• Status: Active Grant

• Current Assignee: Icometrue Company Ltd.
• Original Assignee: Icometrue Company Ltd.
• Inventors: Lee, Jin-Yuan, Lin, Mou-Shiung
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US16/539,024
• Publication Number:
  US 20190372574A1
• Time in Patent Office: 217 Days
• Field of Search: 326 41
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• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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• CPC Class Codes: H10B 63/80 : Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 50/10 : Magnetoresistive devices
• CPC Class Codes: H10N 50/85 : Magnetic active materials

Abstract

A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

Claims

1. A semiconductor IC chip comprising:

a programmable logic circuit configured to be programmed to perform a logic operation, comprising;

a plurality of input points for a first input data set for the logic operation;

a plurality of first non-volatile memory cells configured to store a plurality of resulting values of a look-up table (LUT), each of the plurality of first non-volatile memory cells comprising;

a floating-gate P-type MOS transistor having a gate terminal, comprising a first fin of N-type protruding from a P-type silicon substrate of the semiconductor IC chip and extending in a first direction, and an N-type region in the P-type silicon substrate and directly under the first fin;

a floating-gate MOS device having a gate terminal coupling to the gate terminal of the floating-gate P-type MOS transistor, comprising a protrusion protruding from the P-type silicon substrate, wherein the floating-gate MOS device is configured as a MOS capacitor;

an interconnect extending from the first fin to the protrusion in a second direction, substantially perpendicular to the first direction, wherein the interconnect covers a top and two opposite sidewalls of the first fin and a top and a first sidewall of the protrusion; and

an oxide layer over the P-type silicon substrate, between the interconnect and the first fin and between the interconnect and the protrusion, wherein the oxide layer on the protrusion divides the protrusion into two sides opposite to each other in the first direction, wherein the two sides are doped with impurities, wherein the two sides are configured as a first terminal of the MOS capacitor and the gate terminal of the floating-gate MOS device is configured as a second terminal of the MOS capacitor, wherein the interconnect connects the gate terminals of the floating-gate P-type MOS transistor and floating-gate MOS device, and wherein the interconnect is floating;

a multiplexer configured to select, in accordance with the first input data set, a resulting value from the plurality of resulting values of the look-up table (LUT) as an output data for the logic operation; and

an output point for the output data for the logic operation.

2. The semiconductor IC chip of claim 1, wherein the multiplexer comprises a first set of input points for the first input data set for the logic operation and a second set of input points for a second input data set associated with the plurality of resulting values of the look-up table (LUT), wherein the multiplexer is configured to select, in accordance with the first input data set, the resulting value from the second input data set associated with the plurality of resulting values of the look-up table (LUT) as the output data for the logic operation.

3. The semiconductor IC chip of claim 2 further comprising an inverter having an input point for the resulting value of the plurality of resulting values of the look-up table (LUT) stored in a memory cell of the plurality of first non-volatile memory cells, wherein an input data at the input point of the inverter is configured to be inverted by the inverter as an output data at an output point of the inverter, wherein the output point of the inverter couples to an input point of the second set of input points of the multiplexer, wherein the inverter is on a signal path between the memory cell of the plurality of first non-volatile memory cells and the input point of the second set of input points of the multiplexer.

4. The semiconductor IC chip of claim 1 further comprising a switch and a plurality of second non-volatile memory cells, configured to store a plurality of programming codes configured to control the switch for programmable interconnection of the semiconductor IC chip.

5. The semiconductor IC chip of claim 4 further comprising a first programmable interconnection line and a second programmable interconnection line, each coupling to the switch, wherein the switch is configured to control a connection between the first and second programmable interconnection lines.

6. The semiconductor IC chip of claim 1, wherein the interconnect comprises metal.

7. The semiconductor IC chip of claim 1, wherein the two sides are doped with a plurality of P-type atoms to form two P⁺ regions respectively.

8. The semiconductor IC chip of claim 7, wherein the two P⁺ regions couple to each other.

9. The semiconductor IC chip of claim 1, wherein the floating-gate P-type MOS transistor further comprises a second fin of N-type protruding from the P-type silicon substrate and extending in the first direction, wherein the interconnect further extends over the second fin and further covers a top and two opposite sidewalls of the second fin, wherein the oxide layer is further between the interconnect and the second fin.

10. The semiconductor IC chip of claim 1, wherein the interconnect further covers a second sidewall of the protrusion, wherein the second sidewall is opposite to the first sidewall.

11. The semiconductor IC chip of claim 1, wherein the floating-gate P-type MOS transistor has a gate capacitance between 1 and 10 times of a gate capacitance of the floating-gate MOS device.

12. The semiconductor IC chip of claim 1, wherein the logic operation comprises a NAND operation.

13. The semiconductor IC chip of claim 1, wherein the logic operation comprises addition.

14. The semiconductor IC chip of claim 1, wherein the logic operation comprises multiplication.

15. The semiconductor IC chip of claim 1, wherein the oxide layer is configured for electron tunneling therethrough for erasing the resulting value of the plurality of resulting values of the look-up table (LUT) in a memory cell of the plurality of first non-volatile memory cells.

16. A semiconductor IC chip comprising:

a switch; and

a plurality of non-volatile memory cells configured to store a plurality of programming codes configured to control the switch, each of the plurality of non-volatile memory cells comprising;

a floating-gate P-type MOS transistor having a gate terminal, comprising a first fin of N-type protruding from a P-type silicon substrate of the semiconductor IC chip and extending in a first direction, and an N-type region in the P-type silicon substrate and directly under the first fin;

a floating-gate MOS device having a gate terminal coupling to the gate terminal of the floating-gate P-type MOS transistor, comprising a protrusion protruding from the P-type silicon substrate, wherein the floating-gate MOS device is configured as a MOS capacitor;

an interconnect extending from the first fin to the protrusion in a second direction, substantially perpendicular to the first direction, wherein the interconnect covers a top and two opposite sidewalls of the first fin and a top and a first sidewall of the protrusion; and

an oxide layer over the P-type silicon substrate, between the interconnect and the first fin and between the interconnect and the protrusion, wherein the oxide layer on the protrusion divides the protrusion into two sides opposite to each other in the first direction, wherein the two sides are doped with impurities, wherein the two sides are configured as a first terminal of the MOS capacitor and the gate terminal of the floating-gate MOS device is configured as a second terminal of the MOS capacitor, wherein the interconnect connects the gate terminals of the floating-gate P-type MOS transistor and floating-gate MOS device, and wherein the interconnect is floating.

17. The semiconductor IC chip of claim 16, wherein the interconnect comprises metal.

18. The semiconductor IC chip of claim 16, wherein the floating-gate P-type MOS transistor further comprises a second fin of N-type protruding from the P-type silicon substrate and extending in the first direction, wherein the interconnect further extends over the second fin and further covers a top and two opposite sidewalls of the second fin, wherein the oxide layer is further between the interconnect and the second fin.

19. The semiconductor IC chip of claim 16, wherein the interconnect further covers a second sidewall of the protrusion, wherein the second sidewall is opposite to the first sidewall.

20. The semiconductor IC chip of claim 16, wherein the floating-gate P-type MOS transistor has a gate capacitance between 1 and 10 times of a gate capacitance of the floating-gate MOS device.

21. The semiconductor IC chip of claim 16, wherein the oxide layer is configured for electron tunneling therethrough for erasing a programming code of the plurality of programming codes in a memory cell of the plurality of non-volatile memory cells.

22. The semiconductor IC chip of claim 16 further comprising a first programmable interconnection line and a second programmable interconnection line, each coupling to the switch, wherein the switch is configured to control a connection between the first and second programmable interconnection lines.

23. The semiconductor IC chip of claim 16, wherein the two sides are doped with a plurality of P-type atoms to form two P⁺ regions respectively.

24. The semiconductor IC chip of claim 23, wherein the two P⁺ regions couple to each other.

25. A non-volatile memory cell in a semiconductor IC chip, comprising:

a floating-gate P-type MOS transistor having a gate terminal, comprising a first fin of N-type protruding from a P-type silicon substrate of the semiconductor IC chip and extending in a first direction, and an N-type region in the P-type silicon substrate and directly under the first fin;

a floating-gate MOS device having a gate terminal coupling to the gate terminal of the floating-gate P-type MOS transistor, comprising a protrusion protruding from the P-type silicon substrate, wherein the floating-gate MOS device is configured as a MOS capacitor;

an interconnect extending from the first fin to the protrusion in a second direction, substantially perpendicular to the first direction, wherein the interconnect covers a top and two opposite sidewalls of the first fin and a top and a first sidewall of the protrusion; and

an oxide layer over the P-type silicon substrate, between the interconnect and the first fin and between the interconnect and the protrusion, wherein the oxide layer on the protrusion divides the protrusion into two sides opposite to each other in the first direction, wherein the two sides are doped with impurities, wherein the two sides are configured as a first terminal of the MOS capacitor and the gate terminal of the floating-gate MOS device is configured as a second terminal of the MOS capacitor, wherein the interconnect connects the gate terminals of the floating-gate P-type MOS transistor and floating-gate MOS device, and wherein the interconnect is floating.

26. The non-volatile memory cell of claim 25, wherein the interconnect comprises metal.

27. The non-volatile memory cell of claim 25, wherein the two sides are doped with a plurality of P-type atoms to form two P⁺ regions respectively.

28. The non-volatile memory cell of claim 27, wherein the two P⁺ regions couple to each other.

29. The non-volatile memory cell of claim 25, wherein the floating-gate P-type MOS transistor further comprises a second fin of N-type protruding from the P-type silicon substrate and extending in the first direction, wherein the interconnect further extends over the second fin and further covers a top and two opposite sidewalls of the second fin, wherein the oxide layer is further between the interconnect and the second fin.

30. The non-volatile memory cell of claim 25, wherein the interconnect further covers a second sidewall of the protrusion, wherein the second sidewall is opposite to the first sidewall.

31. The non-volatile memory cell of claim 25, wherein the oxide layer is configured for electron tunneling therethrough for erasing data therein.

32. The non-volatile memory cell of claim 25, wherein the floating-gate P-type MOS transistor has a gate capacitance between 1 and 10 times of a gate capacitance of the floating-gate MOS device.