Method, a non-transitory computer-readable medium, and/or an apparatus for determining whether to order a mask structure
First Claim
1. A method for determining whether to order a mask structure using a processor, the method comprising:
- acquiring a simulation result of an extreme ultraviolet (EUV) pattern layout,the simulation result including a simulated depth of focus (DOF), a simulated energy latitude (EL), a simulated line-edge roughness (LER) area parameter that is less than or equal to a first threshold, and a simulated LER width parameter that is less than or equal to a second threshold,the simulated LER area parameter indicating a roughness of one or more area features in the simulation result of the EUV pattern layout,the simulated LER width parameter indicating a roughness of one or more line features in the simulation result of the EUV pattern layout;
determining a correlation parameter (CP) using the processor based on the simulated DOF, the simulated EL, the simulated LER area parameter, the simulated LER width parameter, and a weighting value for the simulation result,the CP indicating a correlation between the simulation result of the EUV pattern layout and an actual wafer result of the EUV pattern layout;
generating a predicted wafer process window using the processor based on the CP, the predicted wafer process window indicating whether the actual wafer result of the EUV pattern layout will include a patterning defect; and
determining the mask structure is suitable for ordering based on the CP and the predicted wafer process window.
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Abstract
A method for determining whether to order a mask structure using a processor may include acquiring a simulation result of an EUV pattern layout, determining a correlation parameter (CP), generating a predicted wafer process window, and determining the mask structure is suitable for ordering based on the CP and the predicted wafer process window. The processor may determine the CP based on a weighting value and a simulated depth of focus (DOF), a simulated energy latitude (EL), and simulated line-LER area and LER-width parameters in the simulation result. The CP may indicate a correlation between the simulation result of the EUV pattern layout and an actual wafer result of the EUV pattern layout. The predicted wafer process window may be generated using the processor based on the CP. The predicted wafer process window may indicate whether the actual wafer result of the EUV pattern layout will include a patterning defect.
26 Citations
20 Claims
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1. A method for determining whether to order a mask structure using a processor, the method comprising:
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acquiring a simulation result of an extreme ultraviolet (EUV) pattern layout, the simulation result including a simulated depth of focus (DOF), a simulated energy latitude (EL), a simulated line-edge roughness (LER) area parameter that is less than or equal to a first threshold, and a simulated LER width parameter that is less than or equal to a second threshold, the simulated LER area parameter indicating a roughness of one or more area features in the simulation result of the EUV pattern layout, the simulated LER width parameter indicating a roughness of one or more line features in the simulation result of the EUV pattern layout; determining a correlation parameter (CP) using the processor based on the simulated DOF, the simulated EL, the simulated LER area parameter, the simulated LER width parameter, and a weighting value for the simulation result, the CP indicating a correlation between the simulation result of the EUV pattern layout and an actual wafer result of the EUV pattern layout; generating a predicted wafer process window using the processor based on the CP, the predicted wafer process window indicating whether the actual wafer result of the EUV pattern layout will include a patterning defect; and determining the mask structure is suitable for ordering based on the CP and the predicted wafer process window. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A non-transitory computer-readable medium storing computer-executable instructions that, when executed by a processor, cause the processor to perform operations for determining whether to order a mask structure using an electronic apparatus, the operations including:
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acquiring a simulation result of an extreme ultraviolet (EUV) pattern layout using the electronic apparatus, the simulation result including a simulated depth of focus (DOF), a simulated energy latitude (EL), a simulated line-edge roughness (LER) area parameter that is less than or equal to a first threshold, and a simulated LER width parameter that is less than or equal to a second threshold; determining a correlation parameter (CP) using the electronic apparatus based on the simulated DOF, the simulated EL, the simulated LER area parameter, the simulated LER width parameter, and a weighting value for the simulation result, the CP indicating a correlation between the simulation result of the EUV pattern layout and an actual wafer result of the EUV pattern layout; generating a predicted wafer process window using the electronic apparatus based on the CP, the predicted wafer process window indicating whether the actual wafer result of the EUV pattern layout will include a patterning defect; and determining the mask structure is suitable for ordering based on the CP and the predicted wafer process window.
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18. An apparatus for determining whether to order a mask structure, the apparatus comprising:
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a memory; and a processor coupled to the memory, the processor, in response to executing instructions received from the memory, being configured to determine a correlation parameter (CP), based on a simulated depth of focus (DOF), a simulated energy latitude (EL), a simulated line-edge roughness (LER) area parameter, a simulated LER width parameter, and a weighting value, the simulated DOF, the simulated EL, the simulated LER area parameter, the simulated LER width parameter being based on a simulation result of an extreme ultraviolet (EUV) pattern layout, the CP indicating a correlation between the simulation result of the EUV pattern layout and an actual wafer result of the EUV pattern layout, the processor being configured to generate a predicted wafer process window based on the CP, the predicted wafer process window indicating whether the actual wafer result of the EUV pattern layout will include a patterning defect, and the processor being configured to determine the mask structure is suitable for ordering based on the CP and the predicted wafer process window. - View Dependent Claims (19, 20)
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Specification