Multi-purpose events for notification and sequence control in multi-core processor systems

• US 10,599,488 B2
• Filed: 06/29/2016
• Issued: 03/24/2020
• Est. Priority Date: 06/29/2016
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Brown, David A., Jain, Rishabh, Duller, Michael, Schlanger, Erik
• Primary Examiner(s): Truong, Lechi
• Application Number:
  US15/197,436
• Publication Number:
  US 20180004581A1
• Time in Patent Office: 1,364 Days
• Field of Search: 719318
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications

Abstract

Techniques are provided for improving the performance of a constellation of coprocessors by hardware support for asynchronous events. In an embodiment, a coprocessor receives an event descriptor that identifies an event and a logic. The coprocessor processes the event descriptor to configure the coprocessor to detect whether the event has been received. Eventually a device, such as a CPU or another coprocessor, sends the event. The coprocessor detects that it has received the event. In response to detecting the event, the coprocessor performs the logic.

Claims

1. A method comprising:

receiving an event descriptor that identifies a particular event and a logic;

executing an instruction that specifies a plurality of events, including the particular event, to receive;

sending, on one or more wires that are exclusively dedicated for delivering events, said particular event by a device of a CPU to a global event distributor, wherein said global event distributor, a coprocessor, and said CPU reside on a same chip;

selecting, by said global event distributor based on said particular event, a subset plurality of coprocessors from a first plurality of coprocessors of said CPU, wherein said subset plurality of coprocessors contains at least said coprocessor and another coprocessor;

relaying said particular event from said global event distributor to said subset plurality of coprocessors;

waiting until any event of said plurality of events is received;

responsive to detecting said particular event is received, said coprocessor performing said logic.

2. The method of claim 1 wherein said device of said CPU comprises a second coprocessor of said CPU.

3. The method of claim 1 wherein said device of said CPU comprises said coprocessor.

4. The method of claim 1 wherein said receiving said event descriptor comprises receiving said event descriptor onto a descriptor queue.

5. The method of claim 1 wherein:

said logic specifies using a particular resource;

the method further comprises said device of said CPU preparing said particular resource after said receiving said event descriptor.

6. The method of claim 1 wherein said device of said CPU comprises at least one of:

a direct memory access (DMA) controller or a DMA channel.

7. The method of claim 1 further comprising said coprocessor sending, to said global event distributor, a request to subscribe to said particular event.

8. The method of claim 7 further comprising, in response to said relaying said particular event to said subset plurality of coprocessors, said global event distributor automatically canceling said request to subscribe to said particular event.

9. The method of claim 1 wherein:

said sending said particular event consists of sending said particular event through circuitry;

said waiting until any event of said plurality of events is received comprises said coprocessor waits until all events of the plurality of events are received.

10. The method of claim 1 wherein said event descriptor identifies a second event for said coprocessor to send after performing said logic.

11. The method of claim 1 wherein said event descriptor identifies a second event for said coprocessor to receive before performing a logic of another event descriptor.

12. The method of claim 1 further comprising:

receiving a second event descriptor that identifies a second event and a second logic,

wherein the plurality of events comprises the second event;

processing said second event descriptor to configure said coprocessor to detect whether said second event has been received;

wherein said detecting that said particular event is received comprises detecting that said particular event or said second event is received;

wherein said coprocessor performing said logic comprises said coprocessor performing said logic or said second logic based on whether said particular event or said second event was received.

13. The method of claim 1 wherein said sending said particular event comprises said device of said CPU setting or clearing a particular bit of an event register within said coprocessor.

14. The method of claim 13 further comprising:

after said performing said logic, receiving a second event descriptor that identifies said particular event and a second logic;

clearing said particular bit of said event register;

detecting, by said coprocessor, that said particular bit is set after said clearing said particular bit;

responsive to said detecting that said particular bit is set after said clearing, said coprocessor performing said second logic.

15. The method of claim 1 wherein performing said logic comprises said coprocessor sending a second event, wherein said second event is delivered after performing said logic finishes.

16. The method of claim 1 wherein performing said logic comprises said coprocessor sending a second event, wherein said second event is delivered before performing said logic finishes.

17. A system comprising:

a central processing unit (CPU);

a first plurality of coprocessors that are connected to the CPU, including a coprocessor configured to;

receive an event descriptor that identifies a particular event and a logic,

execute an instruction that specifies a plurality of events, including the particular event, to receive by said coprocessor,

wait until any event of said plurality of events is received, and

responsive to detecting said particular event is received, perform said logic;

a global event distributor connected to said first plurality of coprocessors and configured to;

select, based on said particular event, a subset plurality of coprocessors from said first plurality of coprocessors, wherein said subset plurality of coprocessors contains at least said coprocessor and another coprocessor; and

relay said particular event to said subset plurality of coprocessors, wherein said global event distributor, said coprocessor, and said CPU reside on a same chip;

a device connected to the global event distributor and configured to send, on one or more wires that are exclusively dedicated for delivering events, said particular event to said global event distributor.