Resistive memory device having reduced chip size and operation method thereof
First Claim
1. A memory device comprising:
- a voltage generator generating a write word line voltage according to activation of a write enable signal;
a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output word line voltage;
a word line power path connected to the switch circuit to receive the output word line voltage; and
a word line driver driving a word line of the memory device according to a voltage applied to the word line power path, wherein the memory device starts to receive a write command after a certain delay following the activation of the write enable signal, and a write operation is performed on the memory device within an activation period of the write enable signal in response to the received write command,wherein at least one read command is further received during the activation period of the write enable signal, andwherein only a read command is received during a deactivation period of the write enable signal.
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Abstract
A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.
5 Citations
12 Claims
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1. A memory device comprising:
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a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output word line voltage; a word line power path connected to the switch circuit to receive the output word line voltage; and a word line driver driving a word line of the memory device according to a voltage applied to the word line power path, wherein the memory device starts to receive a write command after a certain delay following the activation of the write enable signal, and a write operation is performed on the memory device within an activation period of the write enable signal in response to the received write command, wherein at least one read command is further received during the activation period of the write enable signal, and wherein only a read command is received during a deactivation period of the write enable signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of operating a resistive memory device, the method comprising:
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generating, by a word line driver, a first word line voltage in response to activation of a write enable signal; generating, by the word line driver, a second word line voltage related to a read operation; transferring, by the word line driver, the first word line voltage to a word line power path in response to the activation of the write enable signal; performing a write operation by driving a word line of the resistive memory device by using the first word line voltage, in correspondence with a write command received after a certain delay following the activation of the write enable signal; and performing the read operation by driving the word line by using the first word line voltage, in correspondence with at least one read command received during an activation period of the write enable signal, wherein the word line power path is arranged in common with respect to the first word line voltage and the second word line voltage, and wherein the word line is driven by activating the word line by using the first word line voltage or the second word line voltage. - View Dependent Claims (9, 10)
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11. A method of operating a memory controller controlling a memory device, the method comprising:
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activating, by the memory controller, a write enable signal and providing the write enable signal to the memory device; starting, by the memory controller, transmission of one or more write commands to the memory device, after a certain delay following the activation of the write enable signal; transmitting, by the memory controller, at least one read command during an activation period of the write enable signal; and deactivating, by the memory controller, the write enable signal after completion of the transmission of the one or more write commands and the at least one read command, wherein the one or more write commands and the at least one read command are together transmitted during the same activation period of the write enable signal. - View Dependent Claims (12)
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Specification