Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations

• US 10,600,478 B2
• Filed: 09/05/2018
• Issued: 03/24/2020
• Est. Priority Date: 07/06/2018
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Tzoufras, Michail, Gajek, Marcin, Bozdag, Kadriye Deniz
• Primary Examiner(s): Hidalgo, Fernando
• Application Number:
  US16/122,745
• Publication Number:
  US 20200013455A1
• Time in Patent Office: 566 Days
• Field of Search: 365158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/5607 using magnetic storage elements
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

Claims

1. A memory device comprising:

an array of Multi-Bit Cells (MBCs), the MBCs each including a plurality of cell elements having different sets of state parameter values, wherein a pinned magnetization polarization of a first cell of the plurality of cell elements is opposite a pinned magnetization polarization of a second cell of the plurality of cell elements;

one or more memory circuits configured to;

sequentially apply different successive sets of state programming conditions to a selected plurality of the MBCs, wherein a respective set of state programming conditions programs a corresponding one of the plurality of cell elements to a respective state parameter value;

determine, after applying each of the set of programming conditions, a state change result for the selected plurality of the MBCs; and

determine a read state of the selected plurality of MBCs based on the determined state change results.

2. The memory device of claim 1, wherein the MBCs includes a first Magnetic Tunnel Junction (MTJ) element and a second MTJ element.

3. The memory device of claim 1, wherein the successive set of state programming conditions comprises:

a first predetermined negative potential between bit lines and source lines of the selected plurality of MBCs; and

a second predetermined negative potential between bit lines and source lines of the selected plurality of MBCs, wherein the second predetermined negative potential is more negative than the first predetermined negative potential.

4. The memory device of claim 3, wherein:

the first predetermined negative potential is configured to program a first Magnetic Tunnel Junction (MTJ) element of the selected plurality of MBCs to a first state; and

the second predetermined negative potential is configured to program a second MTJ element of the selected plurality of MBCs to a second state.

5. The memory device of claim 4, wherein:

the first state comprises a parallel state; and

the second state comprises an antiparallel state.

6. The memory device of claim 1, wherein the successive set of state programming conditions comprises:

a first predetermined positive potential between bit lines and source lines of the selected plurality of MBCs; and

a second predetermined positive potential between bit lines and source lines of the selected plurality of MBCs, wherein the second predetermined positive potential is more positive than the first predetermined positive potential.

7. The memory device of claim 5, wherein:

the first predetermined positive potential is configured to program a first Magnetic Tunnel Junction (MTJ) element of the selected plurality of MBCs to a first state; and

the second predetermined positive potential is configured to program a second MTJ element of the selected plurality of MBCs to a second state.

8. The memory device of claim 7, wherein:

the first state comprises an antiparallel state; and

the second state comprises a parallel state.

9. The memory device of claim 1, wherein the one or more memory circuits include:

a word line circuit, a bit line circuit and a source line circuit configured to bias the selected plurality of MBCs with a first set of sense voltage or current levels, and a sense circuit to sense a first instance of a sense level of the selected plurality of MBCs;

the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with a first set of program voltage or current levels;

the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with the first set of sense voltage or current levels, and the sense circuit to sense a second instance of the sense level of the selected plurality of MBCs;

the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with a second set of sense voltage or current levels, and the sense circuit to sense a third instance of the sense level of the selected plurality of MBCs;

the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with a second set of program voltage or current levels;

the word line circuit, the bit line circuit and the source line circuit configured to bias the selected plurality of MBCs with the second set of sense voltage or current levels, and the sense circuit to sense a fourth instance of the sense level of the selected plurality of MBCs; and

a read logic circuit configured to determine the read state of the selected plurality of MBCs based on a presence or absence of a change between the first instance of the sense level and the second instance of the sense level and a presence or absence of a change between the third instance of the sense level and the fourth instance of the sense level.

10. The memory device of claim 1, wherein the sense circuit comprises:

a plurality of current or voltage sources to apply a fixed current or fixed voltage to the selected plurality of MBCs;

a plurality of first switches and first capacitors coupled together and configured to store the first instance of the sense level of the selected plurality of MBCs;

a plurality of second switches and second capacitors coupled together and configured to store the second instance of the sense level and the third instance of the sense level of the selected plurality of MBCs;

a plurality of third switches and third capacitors coupled together and configured to store the fourth instance of the sense level of the selected plurality of MBCs;

a plurality of first comparators coupled to the plurality of first switches and first capacitors and the plurality of second switches and second capacitors and configured to compare the second instance of the sense level to the first instance of the sense level; and

a plurality of second comparators coupled to the plurality of second switches and second capacitors and the plurality of third switches and third capacitors and configured to compare the fourth instance of the sense level to the third instance of the sense level.

11. The memory device of claim 1, wherein the one or more memory circuits are further configured to write the determined state back to the MBCs.

13. The memory device of claim 10, wherein the selected plurality of MBCs includes a computing device readable media word.

14. The memory device of claim 10, wherein the selected plurality of MBCs includes a computing device readable media page.

15. The memory device of claim 10, wherein the selected plurality of MBCs includes a computing device readable media code word.

16. The memory device of claim 10, wherein the one or more circuits are further configured to:

write the determined read state back to the selected plurality of MBCs.

17. The memory device of claim 10, wherein:

the first programming voltage comprises a first negative potential; and

the second programming voltage comprises a second negative potential that is more negative than the first negative potential.

18. The memory device of claim 10, wherein:

the first programming voltage comprises a first positive potential; and

the second programming voltage comprises a second positive potential that is more positive than the first positive potential.

12. A memory device comprising:

a Multi-Bit Cell (MBC) coupled between a bit line and a source line, wherein the multi-MBC includes a first MTJ element, a second MTJ element and a selector coupled in series, wherein the first and second MTJ elements have different low-resistance levels and different high-resistance levels, and wherein the first and second MTJ elements have opposite pinned magnetization polarization orientations;

one or more memory circuits configured to;

receive a read command for a selected plurality of MBCs;

sense for each selected MBC a first sense voltage of the MBC;

program the selected plurality of MBCs using a first program voltage after sensing the first sense voltage, wherein the first MTJ element will be in a first known state after programming;

sense for each selected MBC a second sense voltage of the MBC after programming the MBC using the first program voltage;

compare for each selected MBC the second sense voltage to the first sense voltage, after sensing the second sense voltage, to determine a first resistance change state;

program the selected plurality of MBCs using a second program voltage after sensing the second sense voltage, wherein the state of the second MTJ element will be in a second known state after programming;

sense for each selected MBC a third sense voltage of the MBC after programming the MBC using the second program voltage;

compare for each selected MBC the third sense voltage to the second sense voltage, after sensing the third sense voltage, to determine a second resistance changed state; and

determine a read state of the MBC based on the first resistance change state and the second resistance change state; and

output the read state of the selected plurality of MBCs in response to the received read command.

19. A method of reading a Multi-Bit Cell (MBC) including a first and second MTJ coupled in series and having opposite pinned magnetization polarizations, comprising:

sequentially applying a first and second switching condition to the selected plurality of MBCs, wherein a state of the first MTJ is in a first state after the first switching condition and a state of the second MTJ is in a second state after the second switching condition;

determining, after applying each switching condition, whether a resistive state of the selected plurality of MBCs have changed; and

determining a read state of the selected plurality of MBCs based on whether or not the state of the MBCs changed in response to each applied switching condition.

20. The method according to claim 19, further comprising:

writing the determined read state back to the selected plurality of MBCs.

21. The method according to claim 19, wherein:

the first switching condition comprises a first negative potential voltage; and

the second switching condition comprises a second negative potential voltage that is more negative than the first negative potential voltage.

22. The method according to claim 21, wherein:

the first negative potential voltage is configured to program the first MTJ to a first state and not change the state of the second MTJ; and

the second negative potential voltage is configured to program the second MTJ to a second state.

23. The method according to claim 19, wherein:

the first switching condition comprises a first positive potential voltage; and

the second switching condition comprises a second positive potential voltage that is more positive than the first positive potential voltage.

24. The method according to claim 23, wherein:

the first positive potential voltage is configured to program the first MTJ to a first state and not change the state of the second MTJ; and

the second positive potential voltage is configured to program the second MTJ to a second state.

25. A method of reading from an array of Multi-Bit Cells (MBCs) comprising:

receiving a read command for a selected plurality of MBCs in the array of MBCs, wherein the MBCs each include a first and second MTJ coupled in series and having opposite pinned magnetization polarizations;

sensing for each selected MBC a first instance of a state parameter of the selected plurality of MBCs;

programming the selected plurality of MBCs using a first set of state programming conditions after sensing the first instance of the state parameter, wherein the first MTJ of the selected plurality of MBCs will be in a first state after programming;

sensing for each selected MBC a second instance of the state parameter of the selected plurality of MBCs after programming the selected plurality of MBCs using the first set of state programming conditions;

comparing for each selected MBC the second instance of the state parameter to the first instance of the state parameter, to determine a first state change result for the selected plurality of MBCs;

programming the selected plurality of MBCs using a second set of state programming conditions after sensing the second instance of the state parameter, wherein the second MTJ of the selected plurality of MBCs will be in a second state after programming;

sensing for each selected MBC a third instance of the state parameter of the selected plurality of MBCs after programming the selected plurality of MBCs using the second set of state programming conditions;

comparing for each selected MBC the third instance of the state parameter to the second instance of the state parameter, to determine a second state change result for the selected plurality of MBCs; and

outputting a read state of the selected plurality of MBCs based on the first state change result and the second state change result.

26. The method according to claim 25, wherein:

the first MTJ includes a first resistive state and a second resistive state; and

the second MTJ include a third resistive state and a fourth resistive state.

27. The method according to claim 26, wherein the first resistive state is greater than the third resistive state and the second resistive state is greater than the fourth resistive state.

28. The method according to claim 25, wherein:

the first set of state programming conditions comprise a first negative potential voltage; and

the second set of state programming conditions comprise a second negative potential voltage that is more negative than the first negative potential voltage.

29. The method according to claim 25, wherein:

the first set of state programming conditions comprise a first positive potential voltage; and

the second set of state programming conditions comprise a second positive potential voltage that is more positive than the first positive potential voltage.

30. The method according to claim 25, further comprising:

writing back the read state to the selected plurality of MBCs.