Nanosheet transistors with sharp junctions
First Claim
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1. A method for forming a semiconductor device, the method comprising:
- forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, arranged such that a topmost and a bottommost layer of the nanosheet stack is one of the plurality of sacrificial layers;
forming an oxide recess on a first and a second end of each sacrificial layer;
forming a doped extension region on a first and a second end of each nanosheet;
removing a portion of the nanosheet stack to expose a first and second end of the nanosheet stack and a first and second portion of the substrate;
forming a dielectric layer on the nanosheet stack;
forming a sacrificial gate having a first and a second gate sidewall on the dielectric layer, a top surface of the sacrificial gate covered by a hard mask;
forming a first outer spacer on the first gate sidewall and a first surface of the hard mask;
forming a second outer spacer on the second gate sidewall and a second surface of the hard mask;
forming a first and a second epitaxy on the exposed first and second portion of the substrate;
forming an interlayer dielectric (ILD) on the first and second epitaxy; and
replacing the sacrificial gate and sacrificial layers with a metal gate having a high-k dielectric liner.
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Abstract
A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.
14 Citations
12 Claims
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1. A method for forming a semiconductor device, the method comprising:
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forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, arranged such that a topmost and a bottommost layer of the nanosheet stack is one of the plurality of sacrificial layers; forming an oxide recess on a first and a second end of each sacrificial layer; forming a doped extension region on a first and a second end of each nanosheet; removing a portion of the nanosheet stack to expose a first and second end of the nanosheet stack and a first and second portion of the substrate; forming a dielectric layer on the nanosheet stack; forming a sacrificial gate having a first and a second gate sidewall on the dielectric layer, a top surface of the sacrificial gate covered by a hard mask; forming a first outer spacer on the first gate sidewall and a first surface of the hard mask; forming a second outer spacer on the second gate sidewall and a second surface of the hard mask; forming a first and a second epitaxy on the exposed first and second portion of the substrate; forming an interlayer dielectric (ILD) on the first and second epitaxy; and replacing the sacrificial gate and sacrificial layers with a metal gate having a high-k dielectric liner. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for forming a semiconductor device, the method comprising:
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forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of silicon nanosheets alternating with a plurality of silicon germanium (SiGe) sacrificial layers, arranged such that a topmost and a bottommost layer of the nanosheet stack is one of the plurality of sacrificial layers; oxidizing a first and a second end of each SiGe sacrificial layer to form a silicon oxide (SiO) recess, wherein the oxidizing causes displacement of germanium from the first and second end of each sacrificial layer to a first and second end of each silicon nanosheet, to form a SiGe extension region on the first and second end of each silicon nanosheet; and exposing the nanosheet stack to a dopant for doping the SiGe extension region on the first and second end of each silicon nanosheet. - View Dependent Claims (11, 12)
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Specification