Systems and method for charge balanced semiconductor power devices with fast switching capability

• US 10,600,649 B2
• Filed: 04/13/2018
• Issued: 03/24/2020
• Est. Priority Date: 09/21/2017
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Bolotnikov, Alexander Viktorovich, Losee, Peter Almern, Ghandi, Reza, Lilienfeld, David Alan
• Primary Examiner(s): Malsawma, Lex H
• Application Number:
  US15/953,037
• Publication Number:
  US 20190088479A1
• Time in Patent Office: 711 Days
• Field of Search: None
• CPC Class Codes: H01L 21/0465 using masks
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.

Claims

1. A method of manufacturing a semiconductor device, comprising:

performing a first implantation in a semiconductor layer via ion implantation, forming a first implantation region, wherein the semiconductor layer comprises a top epitaxial (epi) layer, wherein the top epi layer is disposed upon at least one epi layer having a first conductivity type that includes a plurality of charge balance (CB) regions having a second conductivity type to form at least one CB layer; and

performing a second implantation in the semiconductor layer via ion implantation, forming a second implantation region opposite the first implantation region, wherein the first and second implantation regions overlap with one another;

wherein the first and second implantation regions combine to form a connection region extending into the semiconductor layer to at least one of the plurality of CB regions of the at least one CB layer.

2. The method of claim 1, wherein the connection region extends a depth is greater than 3 microns.

3. The method of claim 1, comprising:

applying a first blocking mask to a top surface of the semiconductor layer, wherein the first blocking mask comprises a first set of one or more features; and

removing the first blocking mask from the top surface of the semiconductor layer after the first implantation has been performed.

4. The method of claim 3, comprising:

applying a second blocking mask to the top surface of the semiconductor layer, wherein the second blocking mask comprises a second set of one or more features; and

removing the second blocking mask from the top surface of the semiconductor layer after the second implantation has been performed.

5. The method of claim 4, wherein the first and second blocking masks are each more than 4 microns thick, and wherein each of the features in the first and second sets of one or more features have a width of less than 5 microns.

6. The method of claim 1, comprising:

applying a first blocking mask to a top surface of the semiconductor layer, wherein the first blocking mask comprises a first set of one or more features; and

applying a second blocking mask on top of the first blocking mask, wherein the second blocking mask comprises a second set of one or more features, and wherein the second set of one or more features overlap with the first set of one or more features.

7. The method of claim 6, comprising removing the first and second blocking masks from the top surface of the semiconductor layer after ion implantation.

8. The method of claim 1, wherein the first implantation region is of the second conductivity type and the second implantation region is of the second conductivity type.

9. The method of claim 1, wherein the connection region is of the first conductivity type and the first and second implantation regions are of the second conductivity type.

10. The method of claim 1, wherein the semiconductor device comprises a silicon carbide (SiC) semiconductor device.

11. A charge balanced (CB) device, comprising:

a device layer having a first conductivity type, wherein the device layer comprises a top region having a second conductivity type disposed in a top surface of the device layer;

a first CB layer having the first conductivity type disposed adjacent to the device layer, wherein the first CB layer comprises a first plurality of CB regions having the second conductivity type;

a first connection region comprising a connection region wherein a first implantation region and a second implantation region overlap with one another;

the first implantation region formed by a first implantation adjacent the connection region; and

the second implantation region formed by a second implantation adjacent the connection region, opposite the first implantation region;

wherein the first connection region extends from the top region of the device layer to at least a first CB region of the first plurality of CB regions of the first CB layer.

12. The CB device of claim 11, wherein the connection region is of the second conductivity type and the first and second implantation regions are of the second conductivity type.

13. The CB device of claim 11, wherein the connection region has a width of between approximately 0.5 μ

m and 4 μ

m.

14. The CB device of claim 13, wherein a dopant concentration of the connection region is between approximately 0.5×

10¹⁶ cm<sup>−

3</sup> and 5×

10¹⁶ cm<sup>−

3</sup>.

15. The CB device of claim 11, comprising a second connection region extending from the top region of the device layer to at least a second CB region of the first plurality of CB regions.

16. The CB device of claim 11, wherein the first implantation region is of the second conductivity type and the second implantation region is of the first conductivity type.

17. The CB device of claim 11, wherein the device layer and the CB layer are fabricated from silicon carbide (SiC).

18. The CB device of claim 11, wherein the CB device is a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field effect transistors (JFET), a bipolar junction transistors (BJT), an insulated gate bipolar transistors (IGBT), or a diode.

19. A charge balanced (CB) device, comprising:

at least one epitaxial (epi) layer having a first conductivity type that includes a plurality of charge balance (CB) regions having a second conductivity type to form at least one charge balance (CB) layer, wherein a thickness of each of the plurality of CB regions is less than a thickness of the at least one CB layer;

a top epitaxial layer having the first conductivity type disposed adjacent to the at least one CB layer to form a device layer, wherein the device layer includes a top region having the second conductivity type; and

a connection region comprising a connection region where a first implantation region and a second implantation region overlap with one another;

a first region formed by the first implantation region adjacent the connection region; and

a second region formed by the second implantation region adjacent the connection region, opposite the first region;

wherein the connection region extends from the top region of the device layer to at least one of the plurality of CB regions of the at least one CB layer.

20. The CB device of claim 19, wherein the connection region has a width of between approximately 0.5 μ

m and 4 μ

m, and a dopant concentration between approximately 0.5×

10¹⁶ cm<sup>−

3</sup> and 5×

10¹⁶ cm<sup>−

3</sup>.

21. The CB device of claim 19, wherein the first implantation region is of the second conductivity type and the second implantation region is of the second conductivity type.

22. The CB device of claim 19, wherein the device layer and the CB layer are fabricated from silicon carbide (SiC).

23. The CB device of claim 19, wherein the CB device is a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field effect transistors (JFET), a bipolar junction transistors (BJT), an insulated gate bipolar transistors (IGBT), or a diode.

24. The CB device of claim 19, wherein the first and second implantation regions are formed by introducing one or more dopants into the at least one epi layer using high energy ion implantation.

25. The CB device of claim 19, wherein the first and second implantation regions are formed by introducing dopants injected with implant acceleration energies between approximately 500 keV and approximately 85 MeV.