Semiconductor device and method for manufacturing semiconductor device

• US 10,600,875 B2
• Filed: 06/21/2017
• Issued: 03/24/2020
• Est. Priority Date: 07/01/2016
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Murakawa, Tsutomu, Takeuchi, Toshihiko, Komagata, Hiroki, Sawai, Hiromi, Yamane, Yasumasa, Sambonsuge, Shota, Sugimoto, Kazuya, Yamazaki, Shunpei
• Primary Examiner(s): Wilczewski, Mary A
• Assistant Examiner(s): Chiu, Tsz K
• Application Number:
  US15/628,945
• Publication Number:
  US 20180006124A1
• Time in Patent Office: 1,007 Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

A semiconductor device includes a first conductor; a first insulator thereover; a first oxide thereover; a second oxide thereover; a second conductor and a third conductor that are separate from each other thereover; a third oxide over the first insulator, the second oxide, the second conductor, and the third conductor; a second insulator thereover; a fourth conductor thereover; and a third insulator over the first insulator, the second insulator, and the fourth conductor. The second oxide includes a region where the energy of the conduction band minimum of an energy band is low and a region where the energy of the conduction band minimum of the energy band is high. The energy of the conduction band minimum of the third oxide is higher than that of the region of the second oxide where the energy of the conduction band minimum is low. Side surfaces of the first oxide and the second oxide are covered with the third oxide.

Claims

1. A semiconductor device comprising:

a first conductor;

a first insulator over the first conductor;

a first oxide over the first insulator;

a second oxide over the first oxide;

a second conductor and a third conductor over the second oxide, wherein the second conductor and the third conductor are separate from each other;

a third oxide over the first insulator, the second oxide, the second conductor, and the third conductor;

a second insulator over the third oxide;

a fourth conductor at least part of which overlaps with the second oxide and which is over the second insulator; and

a third insulator over the first insulator, the second insulator, and the fourth conductor,

the second oxide comprising;

a region where an energy of a conduction band minimum of an energy band is low; and

a region where an energy of a conduction band minimum of an energy band is high,

wherein the region where the energy of the conduction band minimum is low includes more carriers than the region where the energy of the conduction band minimum is high,

wherein an energy of a conduction band minimum of the third oxide is higher than the energy of the conduction band minimum of the region of the second oxide where the energy of the conduction band minimum is low, and

wherein side surfaces of the first oxide and the second oxide are covered with the third oxide.

2. The semiconductor device according to claim 1,

wherein the second oxide comprises a first crystal part and a second crystal part,

wherein the first crystal part comprises a plurality of nanocrystals,

wherein the second crystal part comprises a plurality of nanocrystals, and

wherein the plurality of nanocrystals in the first crystal part has c-axis alignment.

3. The semiconductor device according to claim 1, wherein the third oxide has higher crystallinity than the second oxide.

4. The semiconductor device according to claim 1, wherein the third oxide comprises a region having c-axis alignment.

5. The semiconductor device according to claim 1, wherein part of the third oxide is in contact with a top surface of the first insulator.

6. The semiconductor device according to claim 1, wherein part of the third insulator is in contact with a top surface of the first insulator.

7. The semiconductor device according to claim 1,

wherein one side end portion of the second conductor is substantially aligned with one side end portion of the first oxide and one side end portion of the second oxide, and

wherein one side end portion of the third conductor is substantially aligned with the other side end portion of the first oxide and the other side end portion of the second oxide.

8. The semiconductor device according to claim 1,

wherein part of the third oxide is in contact with a top surface of the second oxide in a region where the second conductor and the third conductor do not overlap with the second oxide,

wherein the second insulator is in contact with a top surface of the third oxide, and

wherein part of the third insulator is in contact with a top surface of the second insulator in a region where the fourth conductor does not overlap with the second insulator.

9. A semiconductor device comprising:

a first conductor;

a first insulator over the first conductor;

a first oxide over the first insulator;

a second oxide over the first oxide;

a second conductor and a third conductor over the second oxide, wherein the second conductor and the third conductor are separate from each other;

a third oxide over the first insulator, the second oxide, the second conductor, and the third conductor;

a second insulator over the third oxide;

a fourth conductor at least part of which overlaps with the second oxide and which is over the second insulator; and

a third insulator over the first insulator, the second insulator, and the fourth conductor,

the second oxide comprising;

a first region comprising an element M wherein M is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu; and

a second region comprising one or both of In and Zn,

wherein the first region and the second region are mixed to form a mosaic pattern,

wherein the third oxide comprises In, Zn, and the element M,

wherein the third oxide has a higher atomic ratio of the element M to In than the second oxide, and

wherein side surfaces of the first oxide and the second oxide are covered with the third oxide.

10. The semiconductor device according to claim 9, wherein the first region and the second region have a blurred periphery and a cloud-like composition.

11. The semiconductor device according to claim 9, wherein an atomic ratio of In to the element M and Zn in the second oxide is 4:

2;

3 or in a neighborhood of 4;

2;

3.

12. The semiconductor device according to claim 9, wherein an atomic ratio of In to the element M and Zn in the third oxide is 1:

1;

1 or in a neighborhood of 1;

1;

1.

13. The semiconductor device according to claim 9,

wherein the second oxide comprises a first crystal part and a second crystal part,

wherein the first crystal part comprises a plurality of nanocrystals,

wherein the second crystal part comprises a plurality of nanocrystals, and

wherein the plurality of nanocrystals in the first crystal part has c-axis alignment.

14. The semiconductor device according to claim 9, wherein the third oxide has higher crystallinity than the second oxide.

15. The semiconductor device according to claim 9, wherein the third oxide comprises a region having c-axis alignment.

16. The semiconductor device according to claim 9, wherein part of the third oxide is in contact with a top surface of the first insulator.

17. The semiconductor device according to claim 9, wherein part of the third insulator is in contact with a top surface of the first insulator.

18. The semiconductor device according to claim 9,

wherein one side end portion of the second conductor is substantially aligned with one side end portion of the first oxide and one side end portion of the second oxide, and

wherein one side end portion of the third conductor is substantially aligned with the other side end portion of the first oxide and the other side end portion of the second oxide.

19. The semiconductor device according to claim 9,

wherein part of the third oxide is in contact with a top surface of the second oxide in a region where the second conductor and the third conductor do not overlap with the second oxide,

wherein the second insulator is in contact with a top surface of the third oxide, and

wherein part of the third insulator is in contact with a top surface of the second insulator in a region where the fourth conductor does not overlap with the second insulator.