3D semiconductor device

• US 10,600,888 B2
• Filed: 06/10/2018
• Issued: 03/24/2020
• Est. Priority Date: 04/09/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Primary Examiner(s): Blum, David S
• Application Number:
  US16/004,404
• Publication Number:
  US 20180294343A1
• Time in Patent Office: 653 Days
• Field of Search: 257 43, 257497, 257389, 257499, 257369, 257456, 29456
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 : characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66272 : Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66704 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66901 : with a PN homojunction gate
• CPC Class Codes: H01L 29/732 : Vertical transistors
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/808 : with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1304 : Transistor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/34 : of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/011 : Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/25 : based on bulk electronic defects, e.g. trapping of electrons
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors, contacts, and a first metal layer, where a portion of the first single crystal transistors are interconnected, where the interconnected includes the first metal layer and the contacts, and where the portion of the first single crystal transistors are interconnected forms memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a fourth level overlaying the third level, the fourth level including a plurality of fourth transistors; and a second metal layer overlaying the fourth level, where the plurality of second transistors are aligned to the plurality of first transistors with a less than 40 nm alignment error.

Claims

1. A 3D semiconductor device, the device comprising:

a first level comprising a plurality of first single crystal transistors, contacts, and a first metal layer,

wherein a portion of said first single crystal transistors are interconnected,

wherein said interconnected comprises said first metal layer and said contacts, and

wherein said portion of said first single crystal transistors are interconnected forms memory control circuits;

a second level overlaying said first level, said second level comprising a plurality of second transistors;

a third level overlaying said second level, said third level comprising a plurality of third transistors;

a fourth level overlaying said third level, said fourth level comprising a plurality of fourth transistors;

a second metal layer overlaying said fourth level; and

a memory cell,

wherein said plurality of second transistors are aligned to said plurality of first transistors with a less than 40 nm alignment error,

wherein at least one of said plurality of second transistors comprises a source, a channel, and a drain,

wherein said source, said channel, and said drain have the same dopant type,

wherein said second metal comprises bit lines,

wherein said plurality of second transistors each comprise a region of oxide isolation,

wherein said oxide isolation has a leakage current of less than one picoamp per micron at a device power supply voltage of 1.0 and at 25°

C.,

wherein at least one of said plurality of third transistors comprise polysilicon,

wherein one of said plurality of second transistors is self-aligned to at least one of said third transistors,

wherein said memory cell comprises at least one of said plurality of third transistors,

wherein at least one of said plurality of second transistors at least partially overlays at least a portion of said memory control circuits, and

wherein at least one of said memory control circuits is designed to control said memory cell.

2. The 3D semiconductor device according to claim 1, further comprising:

a connective path,

wherein said connective path connects from at least one of said plurality of second transistors to at least one of said plurality of first transistors,

wherein said connective path comprises a through-layer via, and

wherein said through-layer via has a bottom diameter less of than 400 nm.

3. The 3D semiconductor device according to claim 1,

wherein processing of said first transistors accounts for the thermal processing of said second transistors by adjusting the thermal budget of said first level accordingly.

4. The 3D semiconductor device according to claim 1, further comprising:

a NAND type non-volatile memory array,

wherein said NAND type non-volatile memory array comprises said memory cell.

5. The 3D semiconductor device according to claim 1,

wherein said plurality of second transistors are circumscribed by a first guard ring,

wherein said plurality of third transistors are circumscribed by a second guard ring, and

wherein said second guard ring overlays said first guard ring.

6. The 3D semiconductor device according to claim 1, further comprising:

a first set of external connections underlying said first single crystal layer; and

a second set of external connections overlying said metal layer,

wherein said first set of external connections connect said device to a first external device,

wherein said second set of external connections connect said device to a second external device, and

wherein said first set of external connections comprises a through silicon via (TSV).

7. The 3D semiconductor device according to claim 1,

wherein said fourth level comprises a region of transparent material so to enable alignment of said second metal layer to said first metal layer.

8. A 3D semiconductor device, the device comprising:

a first level comprising a plurality of first single crystal transistors, contacts, and a first metal layer,

wherein a portion of said first single crystal transistors are interconnected,

wherein said interconnected comprises said first metal layer and said contacts, and

wherein said portion of said first single crystal transistors are interconnected forms memory control circuits;

a second level overlaying said first level, said second level comprising a plurality of second transistors;

a third level overlaying said second level, said third level comprising a plurality of third transistors;

a fourth level overlaying said third level, said fourth level comprising a plurality of fourth transistors;

a second metal layer overlaying said fourth level;

a fifth level comprising single crystal, said fifth level overlaying said second metal layer; and

a memory cell,

wherein said plurality of second transistors are aligned to said plurality of first transistors with a less than 40 nm alignment error,

wherein at least one of said plurality of second transistors comprises a source, a channel, and a drain,

wherein said source, said channel, and said drain have the same dopant type,

wherein said second metal comprises bit lines,

wherein said plurality of second transistors each comprise a region of oxide isolation,

wherein said oxide isolation has a leakage current of less than one picoamp per micron at a device power supply voltage of 1.0 and at 25°

C.,

wherein at least one of said plurality of third transistors comprise polysilicon,

wherein one of said plurality of second transistors is self-aligned to at least one of said third transistors,

wherein said memory cell comprises at least one of said plurality of third transistors.

9. The 3D semiconductor device according to claim 8, further comprising:

a connective path,

wherein said connective path connects from at least one of said plurality of second transistors to at least one of said plurality of first transistors,

wherein said connective path comprises a through-layer via, and

wherein said through-layer via has a bottom diameter less of than 400 nm.

10. The 3D semiconductor device according to claim 8,

wherein said fourth level comprises a region of transparent material so to enable alignment through said region to alignment marks.

11. The 3D semiconductor device according to claim 8, further comprising:

a NAND type non-volatile memory array,

wherein said NAND type non-volatile memory array comprises said memory cell.

12. The 3D semiconductor device according to claim 8,

wherein said plurality of second transistors are circumscribed by a first guard ring,

wherein said plurality of third transistors are circumscribed by a second guard ring, and

wherein said second guard ring overlays said first guard ring.

13. The 3D semiconductor device according to claim 8,

wherein at least one of said plurality of second transistors at least partially overlays at least one of said plurality of first transistors.

14. The 3D semiconductor device according to claim 8, further comprising:

a first set of external connections underlying said first single crystal layer; and

a second set of external connections overlying said metal layer,

wherein said first set of external connections connect said device to a first external device,

wherein said second set of external connections connect said device to a second external device, and

wherein said first set of external connections comprises a through silicon via (TSV).

15. A 3D semiconductor device, the device comprising:

a first level comprising a plurality of first single crystal transistors, contacts, and a first metal layer,

wherein a portion of said first single crystal transistors are interconnected,

wherein said interconnected comprises said first metal layer and said contacts, and

wherein said portion of said first single crystal transistors are interconnected forms memory control circuits;

a second level overlaying said first level, said second level comprising a plurality of second transistors;

a third level overlaying said second level, said third level comprising a plurality of third transistors;

a fourth level overlaying said third level, said fourth level comprising a plurality of fourth transistors;

a second metal layer overlaying said fourth level; and

a fifth level comprising single crystal overlaying said second metal layer;

wherein said plurality of second transistors are aligned to said plurality of first transistors with a less than 40 nm alignment error,

wherein at least one of said plurality of second transistors comprises a source, a channel, and a drain,

wherein said source, said channel, and said drain have the same dopant type,

wherein said second metal comprises bit lines,

wherein said plurality of second transistors each comprise a region of oxide isolation,

wherein said oxide isolation has a leakage current of less than one picoamp per micron at a device power supply voltage of 1.0 and at 25°

C.

16. The 3D semiconductor device according to claim 15,

wherein said plurality of second transistors are circumscribed by a first guard ring,

wherein said plurality of third transistors are circumscribed by a second guard ring, and

wherein said second guard ring overlays said first guard ring.

17. The 3D semiconductor device according to claim 15,

wherein at least one of said plurality of third transistors comprises a source, a channel, and a drain,

wherein said source, said channel, and said drain have the same dopant type.

18. The 3D semiconductor device according to claim 15,

wherein said fourth level comprises a region of transparent material so to enable alignment through said region to alignment marks.

19. The 3D semiconductor device according to claim 15, further comprising:

a first set of external connections underlying said first single crystal layer; and

a second set of external connections overlying said second metal layer,

wherein said first set of external connections connects said device to a first external device,

wherein said second set of external connections connects said device to a second external device, and

wherein said first set of external connections comprises a through silicon via (TSV).

20. The 3D semiconductor device according to claim 15, further comprising:

a connective path,

wherein said connective path connects from at least one of said plurality of second transistors to at least one of said plurality of first transistors,

wherein said connective path comprises a through-layer via, and

wherein said through-layer via has a bottom diameter less of than 400 nm.