Nanosheet transistors with thin inner spacers and tight pitch gate

• US 10,600,889 B2
• Filed: 12/22/2017
• Issued: 03/24/2020
• Est. Priority Date: 12/22/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Lee, Choonghyun, Li, Juntao, Xu, Peng
• Primary Examiner(s): Muse, Ismail A
• Assistant Examiner(s): Ausar-El, Charles N
• Application Number:
  US15/852,111
• Publication Number:
  US 20190198645A1
• Time in Patent Office: 823 Days
• Field of Search: 257382
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor structure is provided which includes a nanosheet stack structure on a base. The nanosheet stack structure includes a multilayered nanosheet between adjacent nanosheet layers. The multilayered nanosheet includes one or more first layers of a first material and one or more second layers of a second material, wherein the first material has an etch selectivity different than the second material. The one or more first layers of the multilayered nanosheet are recessed. A first inner spacer includes a third material is formed by depositing the third material into an outer portion of the one or more recessed first layers of the multilayered nanosheet. The one or more second layers of the multilayered nanosheet are recessed. A second inner spacer includes a fourth material which is formed by depositing the fourth material into an outer portion of the one or more recessed second layers of the first multilayered nanosheet.

Claims

1. A method for fabricating a semiconductor structure comprising:

forming a nanosheet stack structure on a semiconductor substrate, wherein the nanosheet stack structure comprises a multilayered nanosheet between adjacent nanosheet layers, and further wherein the multilayered nanosheet comprises one or more first layers of a first material and one or more second layers of a second material, wherein the first material has an etch selectivity different than the second material;

recessing the one or more first layers of the multilayered nanosheet;

forming a first inner spacer comprising a third material, wherein forming the first inner spacer comprises depositing the third material into an outer portion of the one or more recessed first layers of the multilayered nanosheet;

recessing the second layer of the multilayered nanosheet; and

forming a second inner spacer comprising a fourth material, wherein forming the second inner spacer comprises depositing the fourth material into an outer portion of the one or more recessed second layers of the first multilayered nanosheet.

2. The method of claim 1, wherein the multilayered nanosheet comprises at least two layers.

3. The method of claim 1, wherein the multilayered nanosheet comprises at least three layers.

4. The method of claim 1, wherein the multilayered nanosheet is comprised of alternating layers of Si_xGe_y.

5. The method of claim 1, wherein the adjacent nanosheet layers are silicon, and the multilayered nanosheet is comprised of alternating layers of Si_xGe_y.

6. The method of claim 5, wherein the multilayered nanosheet is comprised of Si₆₀Ge₄₀/Si₈₀Ge₂₀/Si₆₀Ge₄₀ layers.

7. The method of claim 1, wherein the step of forming the first inner spacer further comprises:

depositing the third material on an exterior surface of the semiconductor substrate and the nanosheet stack structure including the outer portion of the one or more recessed first layers of the multilayered nanosheet; and

etching back the third material to expose the exterior surface of the semiconductor substrate and the adjacent nanosheet layers of the nanosheet stack structure.

8. The method of claim 7, wherein the step of forming the second inner spacer further comprises:

depositing the fourth material on the exterior surface of the semiconductor substrate and the nanosheet stack structure including the outer portion of the one or more recessed second layers of the multilayered nanosheet; and

etching back the fourth material to expose the exterior surface of the semiconductor substrate and the adjacent nanosheet layers of the nanosheet stack structure.

9. The method of claim 1, further comprising forming a cladding spacer and a dummy gate around the nanosheet stack structure prior to recessing steps.

10. The method of claim 9, further comprising selectively removing the dummy gate.

11. The method of claim 10, further comprising forming a replacement metal gate.

12. The method of claim 11, further comprising forming a gate dielectric layer prior to forming the replacement metal gate.

13. The method of claim 12, further comprising forming at least one interlayer dielectric and at least one source/drain region after the step of forming the second inner spacer.

14. The method of claim 1, further comprising forming isolation layers in a surface region of a base adjacent to the nanosheet stack structure.

15. The method of claim 14, wherein a first and second source/drain regions are disposed on the isolation layers and isolated from the base by the isolation layers.

16. The method of claim 1, wherein a base comprises a semiconductor substrate.

17. The method of claim 16, wherein the semiconductor substrate is comprised of silicon.