Self-repairing field effect transisitor
First Claim
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1. A device comprising:
- a plurality of source contacts within a field effect transistor;
a plurality of field effect transistor cells within the field effect transistor, wherein each cell includes a corresponding source contact;
a source interconnect within the field effect transistor; and
a plurality of source fuse links disposed between the source interconnect and corresponding ones of the plurality of source contacts in corresponding trenches through an encapsulate layer, wherein a top of a gate of at least one of the plurality of field effect transistor cell is below the bottom of the encapsulate layer, wherein the encapsulate layer is disposed between the source interconnect and the plurality of source contacts within the field effect transistor, and wherein each source contact is coupled to the source interconnect by a given one of the plurality of source fuse links configured to blow in response to a high current.
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Abstract
A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.
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Citations
16 Claims
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1. A device comprising:
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a plurality of source contacts within a field effect transistor; a plurality of field effect transistor cells within the field effect transistor, wherein each cell includes a corresponding source contact; a source interconnect within the field effect transistor; and a plurality of source fuse links disposed between the source interconnect and corresponding ones of the plurality of source contacts in corresponding trenches through an encapsulate layer, wherein a top of a gate of at least one of the plurality of field effect transistor cell is below the bottom of the encapsulate layer, wherein the encapsulate layer is disposed between the source interconnect and the plurality of source contacts within the field effect transistor, and wherein each source contact is coupled to the source interconnect by a given one of the plurality of source fuse links configured to blow in response to a high current. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit comprising:
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continuous drain region; a gate region disposed above said continuous drain region, wherein a first portion of the gate region is formed as a first plurality of substantially parallel elongated structures and a second portion of the gate region is formed as a second plurality of substantially parallel elongated structures that are perpendicular to the first plurality of substantially parallel elongated structures; a plurality of source regions disposed proximate a periphery of the gate region between the first and second plurality of substantially parallel elongated structures; a plurality of body regions disposed between said continuous drain region and the plurality of source regions and between the first and second plurality of substantially parallel elongated structures; a gate insulator region disposed between the gate region and the plurality of source regions, between the gate region and the plurality of body regions and between the gate region and said continuous drain region; a plurality of source contacts, wherein each source contact is coupled to a corresponding source region and body region; a source interconnect; a dielectric layer disposed between the plurality of source contacts and the source interconnect; and a plurality of source fuse links disposed in corresponding trenches through the dielectric layer, wherein at least a portion of a top of the gate region is below the bottom of the dielectric layer, wherein each source fuse link couples a. given source contact to the source interconnect and that result in a break in a high current path when blown. - View Dependent Claims (12, 13, 14, 15)
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16. A device comprising:
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a plurality of source regions within a field effect transistor; a unitary drain region within the field effect transistor; a unitary gate region within the field effect transistor; a plurality of source contacts within the field effect transistor, wherein the plurality of source contacts are coupled to corresponding ones of the plurality of source regions; a unitary source interconnect within the field effect transistor; and a plurality of source fuse links within the field effect transistor, wherein the plurality of source fuse links are coupled between the unitary source interconnect and corresponding ones of the plurality of source contacts, and wherein a first one of the plurality of source fuse links electrically isolates a first one of the plurality of source contacts from a. second one of the plurality of source contacts when blown.
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Specification