Self-repairing field effect transisitor

• US 10,600,902 B2
• Filed: 02/13/2008
• Issued: 03/24/2020
• Est. Priority Date: 02/13/2008
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix LLC (Vishay Intertechnology Incorporated)
• Inventors: Xu, Robert
• Primary Examiner(s): Pizarro, Marcos D.
• Assistant Examiner(s): Tang, Sue
• Application Number:
  US12/030,719
• Publication Number:
  US 20090200578A1
• Time in Patent Office: 4,423 Days
• Field of Search: 257209, 257341, 257401, 257E29027, 257E29066, 257E2926, 257E21435, 257173, 257529, 257 48, 257 50, 257179, 257620, 257665, 257797, 257E21532, 438132, 438251, 438281, 438333, 438467, 438601, 438FOR 433
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.

Claims

1. A device comprising:

a plurality of source contacts within a field effect transistor;

a plurality of field effect transistor cells within the field effect transistor, wherein each cell includes a corresponding source contact;

a source interconnect within the field effect transistor; and

a plurality of source fuse links disposed between the source interconnect and corresponding ones of the plurality of source contacts in corresponding trenches through an encapsulate layer, wherein a top of a gate of at least one of the plurality of field effect transistor cell is below the bottom of the encapsulate layer, wherein the encapsulate layer is disposed between the source interconnect and the plurality of source contacts within the field effect transistor, and wherein each source contact is coupled to the source interconnect by a given one of the plurality of source fuse links configured to blow in response to a high current.

2. The field effect transistor device of claim 1, wherein each source fuse link includes a cavity.

3. The field effect transistor device of claim 1, wherein a corresponding source fuse link blows during a high current event in a defective field effect transistor cell.

4. The field of transistor device of claim 1, wherein a source fuse link disables a corresponding field effect transistor cell when there is a source-to-drain short in the particular field effect transistor cell.

5. The field effect transistor device of claim 1, wherein a source fuse link disables a corresponding field effect transistor cell when there is a gate-to-source short in the particular field effect transistor cell.

6. The field effect transistor device of claim 1, wherein:

the plurality of source contacts comprise a metal having a relative high melting point; and

the plurality of source fuse links comprise a metal having a relatively low melting point.

7. The field effect transistor device of claim 1, wherein the plurality of field effect transistor cells comprise approximately five hundred to five billion field effect transistor cells.

8. The field effect transistor device of claim 1, wherein the field effect transistor cells comprise planar metal-oxide-semiconductor field effect transistor cells.

9. The field effect transistor device of claim 1, wherein the field effect transistor cells comprise vertical metal-oxide-semiconductor field effect transistor cells.

10. The field effect transistor device of claim 1, wherein he source contacts, source fuse links and source interconnect are aligned in a axis perpendicular to a fabrication surface of the field effect transistor device.

11. An integrated circuit comprising:

continuous drain region;

a gate region disposed above said continuous drain region, wherein a first portion of the gate region is formed as a first plurality of substantially parallel elongated structures and a second portion of the gate region is formed as a second plurality of substantially parallel elongated structures that are perpendicular to the first plurality of substantially parallel elongated structures;

a plurality of source regions disposed proximate a periphery of the gate region between the first and second plurality of substantially parallel elongated structures;

a plurality of body regions disposed between said continuous drain region and the plurality of source regions and between the first and second plurality of substantially parallel elongated structures;

a gate insulator region disposed between the gate region and the plurality of source regions, between the gate region and the plurality of body regions and between the gate region and said continuous drain region;

a plurality of source contacts, wherein each source contact is coupled to a corresponding source region and body region;

a source interconnect;

a dielectric layer disposed between the plurality of source contacts and the source interconnect; and

a plurality of source fuse links disposed in corresponding trenches through the dielectric layer, wherein at least a portion of a top of the gate region is below the bottom of the dielectric layer, wherein each source fuse link couples a. given source contact to the source interconnect and that result in a break in a high current path when blown.

12. The integrated circuit of Claim 11, wherein each source fuse link includes a cavity adapted to concentrate heat.

13. The integrated circuit of Claim 11, wherein each source fuse link comprises metal having a cavity extending substantially from the corresponding source contact to the source interconnect.

14. The integrated circuit of Claim 11, wherein each source fuse link comprises metal having a cavity substantially in a middle of the source fuse link.

15. The integrated circuit of Claim 11, wherein each source fuse link comprises metal and is adapted to be blown by a failure mode level of current.

16. A device comprising:

a plurality of source regions within a field effect transistor;

a unitary drain region within the field effect transistor;

a unitary gate region within the field effect transistor;

a plurality of source contacts within the field effect transistor, wherein the plurality of source contacts are coupled to corresponding ones of the plurality of source regions;

a unitary source interconnect within the field effect transistor; and

a plurality of source fuse links within the field effect transistor, wherein the plurality of source fuse links are coupled between the unitary source interconnect and corresponding ones of the plurality of source contacts, and wherein a first one of the plurality of source fuse links electrically isolates a first one of the plurality of source contacts from a. second one of the plurality of source contacts when blown.