Semiconductor device including a power transistor device and bypass diode

• US 10,600,903 B2
• Filed: 09/20/2013
• Issued: 03/24/2020
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Van Brunt, Edward Robert, Pala, Vipindas, Cheng, Lin
• Primary Examiner(s): Parker, Allen L
• Assistant Examiner(s): Vu, Pauline
• Application Number:
  US14/032,919
• Publication Number:
  US 20150084118A1
• Time in Patent Office: 2,377 Days
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode

Abstract

A semiconductor device includes a vertical FET device and a Schottky bypass diode. The vertical FET device includes a gate contact, a source contact, and a drain contact. The gate contact and the source contact are separated from the drain contact by at least a drift layer. The Schottky bypass diode is coupled between the source contact and the drain contact and monolithically integrated adjacent to the vertical FET device such that a voltage placed between the source contact and the drain contact is distributed throughout the drift layer by the Schottky bypass diode in such a way that a voltage across each one of a plurality of P-N junctions formed between the source contact and the drain contact within the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction.

Claims

1. A semiconductor device comprising:

a substrate;

a drift layer on the substrate;

a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) comprising;

at least four junction implants in the drift layer opposite the substrate such that the at least four junction implants are separated from one another by a portion of the drift layer;

a gate oxide layer on the drift layer opposite the substrate such that the gate oxide layer at least partially overlaps each one of the at least four junction implants;

a gate contact on the gate oxide layer;

source contacts on the drift layer and above each of the at least four junction implants; and

a drain contact on the substrate; and

junction barrier Schottky bypass diodes comprising a Schottky contact separate from the source contacts on the drift layer opposite the substrate such that the Schottky contact only partially overlaps and runs between two of the at least four junction implants, and is laterally disposed between the source contacts.

2. The semiconductor device of claim 1 wherein a total area of each junction barrier Schottky bypass diode of the junction barrier Schottky bypass diodes is between 1.0 μ

m² and 10.0 μ

m².

3. The semiconductor device of claim 1 wherein the substrate and the drift layer comprise silicon carbide.

4. A semiconductor device comprising:

a substrate;

a drift layer on the substrate;

a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) comprising;

at least four junction implants in the drift layer opposite the substrate such that the at least four junction implants are separated from one another by a portion of the drift layer;

a gate oxide layer on the drift layer opposite the substrate such that the gate oxide layer at least partially overlaps each one of the at least four junction implants;

a gate contact on the gate oxide layer;

source contacts on the drift layer and above each of the at least four junction implants; and

a drain contact on the substrate;

a first junction barrier Schottky bypass diode comprising a first Schottky contact separate from the source contacts on the drift layer opposite the substrate such that the first Schottky contact only partially overlaps and runs between two of the at least four junction implants, and is disposed between the source contacts; and

a second junction barrier Schottky bypass diode comprising a second Schottky contact separate from the source contacts on the drift layer opposite the substrate such that the second Schottky contact only partially overlaps and runs between two of the at least four junction implants, and is laterally disposed between the source contacts.

5. The semiconductor device of claim 4 wherein:

a doping concentration of the substrate is between about 1×

10¹⁸ cm<sup>−

3</sup> and 1×

10²⁰ cm<sup>−

3</sup>; and

a doping concentration of the drift layer is between about 3×

10¹⁴ cm<sup>−

3</sup> and 1.5×

10¹⁶ cm<sup>−

3</sup>.

6. The semiconductor device of claim 4 wherein the first Schottky contact and the second Schottky contact comprise a low barrier height Schottky metal.

7. The semiconductor device of claim 4 wherein a total area of the first junction barrier Schottky bypass diode and the second junction barrier Schottky bypass diode is between 1.0 μ

m² and 10.0 μ

m².

8. The semiconductor device of claim 4 wherein the substrate and the drift layer comprise silicon carbide.

9. A method for manufacturing a semiconductor device comprising:

providing a substrate;

providing a drift layer on the substrate;

providing a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) by;

implanting at least four junction implants in the drift layer opposite the substrate such that the at least four junction implants are separated from one another by a portion of the drift layer;

providing a gate oxide layer on the drift layer opposite the substrate such that the gate oxide layer at least partially overlaps each one of the at least four junction implants;

providing a gate contact on the gate oxide layer;

providing source contacts on the drift layer and above each of the at least four junction implants; and

providing a drain contact on the substrate; and

providing junction barrier Schottky bypass diodes by;

providing Schottky contacts separate from the source contacts on the drift layer opposite the substrate such that each of the Schottky contacts only partially overlaps and runs between two of the at least four junction implants, and is laterally disposed between the source contacts; and

providing a cathode on the substrate opposite the drift layer, wherein the cathode is coupled to the drain contact.

10. The method of claim 9 wherein:

a doping concentration of the substrate is between about 1×

10¹⁸ cm<sup>−

3</sup> and 1×

10²⁰ cm<sup>−

3</sup>; and

a doping concentration of the drift layer is between about 3×

10¹⁴ cm<sup>−

3</sup> and 1.5×

10¹⁶ cm<sup>−

3</sup>.

11. The method of claim 9 wherein the Schottky contacts comprise a low-barrier height Schottky metal.