Self-clocking sampler with reduced metastability
First Claim
1. A self-clocked sampler system, comprising:
- a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals;
a detection circuit that is coupled to the sampler circuit and configured to;
pre-charge the sampled signals when the clock signal is at a second voltage level;
detect a voltage level of a first one of the sampled signals by a first threshold adjusted inverter, wherein a threshold voltage of the first threshold adjusted inverter is entirely outside of a transition voltage range of the sampler circuit;
detect a voltage level of a second one of the sampled signals by a second threshold adjusted inverter, wherein a threshold voltage of the second threshold adjusted inverter is entirely outside of the transition voltage range of the sampler circuit; and
in response to one of the detected voltage levels of the first and second sampled signals transitioning from the second voltage level to the first voltage level, a NAND gate or a NOR gate coupled to outputs of the first and second inverters transitions an output signal from the first voltage level to the second voltage level; and
a feedback circuit configured to receive the output signal and generate the clock signal.
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Abstract
A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.
9 Citations
18 Claims
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1. A self-clocked sampler system, comprising:
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a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals; a detection circuit that is coupled to the sampler circuit and configured to; pre-charge the sampled signals when the clock signal is at a second voltage level; detect a voltage level of a first one of the sampled signals by a first threshold adjusted inverter, wherein a threshold voltage of the first threshold adjusted inverter is entirely outside of a transition voltage range of the sampler circuit; detect a voltage level of a second one of the sampled signals by a second threshold adjusted inverter, wherein a threshold voltage of the second threshold adjusted inverter is entirely outside of the transition voltage range of the sampler circuit; and in response to one of the detected voltage levels of the first and second sampled signals transitioning from the second voltage level to the first voltage level, a NAND gate or a NOR gate coupled to outputs of the first and second inverters transitions an output signal from the first voltage level to the second voltage level; and a feedback circuit configured to receive the output signal and generate the clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computer-implemented method, comprising:
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pre-charging sampled signals when a clock signal is at a second voltage level; sampling input signals when the clock signal is at a first voltage level to drive the sampled signals; detecting a voltage level of a first one of the sampled signals by a first threshold adjusted inverter, wherein a threshold voltage of the first threshold adjusted inverter is entirely outside of a transition voltage range of the sampler circuit; detecting a voltage level of a second one of the sampled signals by a second threshold adjusted inverter, wherein a threshold voltage of the second threshold adjusted inverter is entirely outside of the transition voltage range of the sampler circuit; transitioning, by a NAND gate or a NOR gate coupled to outputs of the first and second inverters, an output signal from the first voltage level to the second voltage level in response to one of the detected voltage levels of the first and second sampled signals transitioning from the second voltage level to the first voltage level; and generating the clock signal by a feedback circuit that receives the output signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification