Semiconductor device having temperature circuit that sets temperature ranges and is disabled upon power supply transition

• US 10,605,672 B2
• Filed: 11/06/2017
• Issued: 03/31/2020
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Walker, Darryl G.
• Primary Examiner(s): Jagan, Mirellys
• Application Number:
  US15/804,944
• Publication Number:
  US 20180058944A1
• Time in Patent Office: 876 Days
• Field of Search: 374170, 374163, 374100
• CPC Class Codes: G01K 13/00 Thermometers specially adapted for specific purposes
• CPC Class Codes: G01K 3/005 Circuits arrangements for indicating a predetermined temperature fire detection G08B17/00
• CPC Class Codes: G01K 7/00 Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat giving results other than momentary value of temperature G01K3/00 ; Power supply therefor, e.g. using thermoelectric elements
• CPC Class Codes: G01K 7/01 using semiconducting elements having PN junctions G01K7/02, G01K7/16, G01K7/30 take precedence
• CPC Class Codes: G01K 7/16 using resistive elements resistive elements per se H01C, H01L
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A device can include a temperature circuit that can selectively set one of a plurality of temperature ranges. Each temperature range can have a temperature range upper limit value and a temperature range lower limit value. The temperature circuit can be disabled in response to a detection of a transition in a power supply voltage. In some embodiments, the temperature circuit can also be enabled a predetermined time period after the detection of the transition in the power supply voltage.

Claims

1. A device, comprising:

a temperature circuit, wherein the temperature circuit is configured to selectively set one of a plurality of temperature ranges, each temperature range having a temperature range upper limit value and a temperature range lower limit value;

wherein the temperature circuit is configured to be disabled in response to a detection of a transition in a power supply voltage.

2. The device of claim 1, wherein the temperature circuit includes a first temperature sensor circuit configured to set the temperature range upper limit value;

and a second temperature sensor circuit configured to set the temperature range lower limit value.

3. The device of claim 1, wherein:

the device is a processor.

4. The device of claim 1, wherein:

the transition in the power supply voltage is a transition from a low paten to a high level that energizes the device.

5. The device of claim 1, wherein:

the device is a dynamic random access memory.

6. The device of claim 1, wherein:

the device is a semiconductor device.

7. The device of claim 1, wherein:

adjacent ones of the plurality of temperature ranges overlap.

8. The device of claim 7, wherein:

the temperature range lower limit value of an upper adjacent one of the temperature ranges is a lower temperature value than the temperature range upper limit value of a lower adjacent one of the temperature ranges.

9. The device of claim 1, wherein:

the temperature circuit is configured to be enabled a predetermined time period after the detection of the transition in the power supply voltage.

10. The device of claim 9, further including:

a power up circuit configured to detect the transition in the power supply voltage, wherein the power up circuit is configured to provide a power up signal and the temperature circuit is configured to be disabled in response to the power up signal having a first power up logic level.

11. The device of claim 10, wherein:

the temperature circuit is configured to be enabled in response to the power up signal having a second power up logic level.

12. The device of claim 1, further including:

a value providing circuit, wherein the value providing circuit is configured to provide a value, and the value selectively sets the one of the plurality of temperature ranges, wherein the value is set to a first value in response to the detection of the transition in the power supply voltage.

13. The device of claim 12, wherein:

the temperature circuit is configured to be enabled a predetermined first time period after the detection of the transition of the power supply voltage and the value provided by the value providing circuit changes to a second value when the temperature of the device is outside the one of the plurality of temperature windows.

14. The device of claim 13, further including:

a power up circuit configured to detect the transition in the power supply voltage, wherein the power up circuit is configured to provide a power up signal and the temperature circuit is configured to be disabled in response to the power up signal having a first power up logic level and the temperature circuit is configured to be enabled in response to the power up signal having a second power up logic level.

15. The device of claim 1, further including:

a latch circuit configured to provide a latched performance parameter signal to a performance parameter adjusted circuit, wherein the latch circuit is configured to set the latched performance parameter signal to a predetermined logic level in response to the detection of the transition in the power supply signal.

16. The device of claim 15, wherein:

the latch circuit is coupled to receive load signal and a performance parameter signal, the latch circuit being configured to latch the performance parameter signal to provide the latched performance parameter signal in response to the load signal, and the load signal is generated a predetermined time after the detection of the transition in the power supply voltage.

17. The device of claim 16, further including:

a performance parameter table, wherein the performance parameter table is configured to provide a performance parameter signal that is selected based on the value provided by the value providing circuit.

18. The device of claim 17, wherein the performance parameter table includes a plurality of non-volatile memory cells.

19. The device of claim 17, wherein the performance parameter table is coupled to receive a read signal, and the performance parameter table is configured to provide the performance parameter signal based on the value provided by the value providing circuit in response to the read signal.

20. The device of claim 19, the read signal is generated a predetermined period after the detection of the transition in the power supply voltage.