High data rate integrated circuit with transmitter configuration

• US 10,605,767 B2
• Filed: 12/16/2015
• Issued: 03/31/2020
• Est. Priority Date: 12/18/2014
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Fife, Keith G., Yang, Jungwook
• Primary Examiner(s): Eom, Robert J
• Application Number:
  US14/971,173
• Publication Number:
  US 20160178566A1
• Time in Patent Office: 1,567 Days
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A high data rate integrated circuit, such as an integrated circuit including a large sensor array, may be implemented using clock multipliers in individual power domains, coupled to sets of transmitters, including a transmitter pair configuration. Reference clock distribution circuitry on the integrated circuit distributes a relatively low speed reference clock. In a transmitter pair configuration, each pair comprises a first transmitter and a second transmitter in a transmitter power domain. Also, each pair of transmitters includes a clock multiplier connected to the reference clock distribution circuitry, and disposed between the first and second transmitters, which produces a local transmit clock.

Claims

1. A device, comprising:

an integrated circuit sensor array chip on a substrate, the integrated circuit sensor array chip including;

a sensor array on the substrate comprising chemical field-effect transistor (chemFET) sensors;

a clock distribution circuitry on the substrate including;

a clock input buffer coupled to a reference signal source;

a plurality of transmitter pairs;

each transmitter pair having a phase locked loop disposed between and coupled to each transmitter of a transmitter pair, wherein each transmitter of each transmitter pair is coupled to a respective corresponding pair of output pads; and

a transmitter control block coupled to each transmitter, wherein the transmitter control block includes clock selector circuitry for selecting a reference clock signal or a local transmit clock signal; and

a multiple power domain circuit system on the substrate, wherein the multiple power domain circuit system includes a separate power domain for each of an analog circuitry component, a digital circuitry component and a transmitter circuitry component.

2. The device of claim 1, wherein the plurality of transmitters includes at least 20 transmitters capable of transmission at data rate greater than 1 Gb per second, and configured in at least 10 pairs.

3. The device of claim 1, further comprising an individual power domain for the phase locked loop disposed on the substrate.

4. The device of claim 3, wherein the individual power domain includes respectively:

a power trace and a ground trace coupled to the phase locked loop; and

a power input pad and a ground input pad coupled to the power trace and ground trace.

5. The device of claim 3, wherein the individual power domain includes electrostatic discharge circuits.

6. The device of claim 3, wherein circuit elements in the individual power domain of the phase locked loop are electrically isolated from circuit elements of other power domains.

7. The device of claim 1, wherein the clock distribution circuitry includes duty cycle correction buffers to correct distortion of the reference clock signal.

8. The device of claim 1, wherein the phase locked loop provides a corresponding local transmit clock signal that has a frequency that is a multiple of a reference clock signal frequency.

9. The device of claim 1, wherein the phase locked loop further includes a low pass filter.

10. The device of claim 1, wherein the sensor array comprising chemical field-effect transistor (chemFET) sensors is a 660 megapixel sensor array.

11. The device of claim 1, wherein each circuitry component of the multiple power domain circuit system includes a power trace and a ground trace connected to each respective circuitry component.

12. The device of claim 11, wherein each power trace and each ground trace connected to each respective circuitry component is respectively connected to at least one power pad at least one ground pad.