High data rate integrated circuit with transmitter configuration
First Claim
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1. A device, comprising:
- an integrated circuit sensor array chip on a substrate, the integrated circuit sensor array chip including;
a sensor array on the substrate comprising chemical field-effect transistor (chemFET) sensors;
a clock distribution circuitry on the substrate including;
a clock input buffer coupled to a reference signal source;
a plurality of transmitter pairs;
each transmitter pair having a phase locked loop disposed between and coupled to each transmitter of a transmitter pair, wherein each transmitter of each transmitter pair is coupled to a respective corresponding pair of output pads; and
a transmitter control block coupled to each transmitter, wherein the transmitter control block includes clock selector circuitry for selecting a reference clock signal or a local transmit clock signal; and
a multiple power domain circuit system on the substrate, wherein the multiple power domain circuit system includes a separate power domain for each of an analog circuitry component, a digital circuitry component and a transmitter circuitry component.
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Abstract
A high data rate integrated circuit, such as an integrated circuit including a large sensor array, may be implemented using clock multipliers in individual power domains, coupled to sets of transmitters, including a transmitter pair configuration. Reference clock distribution circuitry on the integrated circuit distributes a relatively low speed reference clock. In a transmitter pair configuration, each pair comprises a first transmitter and a second transmitter in a transmitter power domain. Also, each pair of transmitters includes a clock multiplier connected to the reference clock distribution circuitry, and disposed between the first and second transmitters, which produces a local transmit clock.
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Citations
12 Claims
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1. A device, comprising:
an integrated circuit sensor array chip on a substrate, the integrated circuit sensor array chip including; a sensor array on the substrate comprising chemical field-effect transistor (chemFET) sensors; a clock distribution circuitry on the substrate including; a clock input buffer coupled to a reference signal source; a plurality of transmitter pairs;
each transmitter pair having a phase locked loop disposed between and coupled to each transmitter of a transmitter pair, wherein each transmitter of each transmitter pair is coupled to a respective corresponding pair of output pads; anda transmitter control block coupled to each transmitter, wherein the transmitter control block includes clock selector circuitry for selecting a reference clock signal or a local transmit clock signal; and a multiple power domain circuit system on the substrate, wherein the multiple power domain circuit system includes a separate power domain for each of an analog circuitry component, a digital circuitry component and a transmitter circuitry component. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
Specification