Mask pattern verification method

• US 10,606,165 B2
• Filed: 08/09/2018
• Issued: 03/31/2020
• Est. Priority Date: 02/08/2018
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Toriu, Yayori, Kajiwara, Masanari, Nakajima, Fumiharu
• Primary Examiner(s): Tat, Binh C
• Application Number:
  US16/100,122
• Publication Number:
  US 20190243232A1
• Time in Patent Office: 600 Days
• Field of Search: 716 50- 56
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 7/70441 Optical proximity correction [OPC]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

According to one embodiment, a mask pattern verification method includes: calculating mask pattern data; calculating an optical image and a resist image; calculating a first feature amount and a second feature amount, using a plurality of algorithms; in each of the plurality of algorithms, comparing the first feature amount with a first threshold, and detecting a critical point candidate in a first pattern; in each of the plurality of algorithms, comparing the second feature amount with a second threshold, and detecting a critical point in the first pattern; and selecting at least one of the plurality of algorithms, and displaying a detection result of the critical point corresponding to a selected algorithm.

Claims

1. A mask pattern verification method performed in a device including a processor, a memory, and a display, the method comprising:

receiving circuit pattern data and optical proximity correction (OPC) condition data from an external device;

storing the circuit pattern data and the OPC condition data in the memory;

calculating, by the processor, mask pattern data based on OPC processing using the circuit pattern data and the OPC condition data;

storing the mask pattern data in the memory;

calculating, by the processor, an optical image and a resist image based on the mask pattern data;

storing the optical image and the resist image in the memory;

calculating, by the processor, a first feature amount regarding a first pattern of the resist image, using a plurality of algorithms;

comparing, by the processor, the first feature amount with a first threshold in each of the plurality of algorithms, and detecting the first pattern as a critical point candidate based on a result of the comparison between the first feature amount and the first threshold in each of the plurality of algorithms;

calculating, by the processor, a second feature amount based on a second pattern that is adjacent to the first pattern detected as the critical point candidate, using the plurality of algorithms;

comparing, by the processor, the second feature amount with a second threshold, and detecting a critical point based on a result of the comparison between the second feature amount and the second threshold;

selecting at least one of the plurality of algorithms; and

displaying, on the display, a detection result of the critical point corresponding to a selected algorithm.

2. The method according to claim 1, wherein the plurality of algorithms include at least one of an algorithm based on a critical dimension (CD) value, an algorithm based on a normalized image log slope (NILS) value, an algorithm based on a peak intensity value of an optical image intensity distribution, and an algorithm based on an integrated intensity value of the optical image intensity distribution.

3. The method according to claim 1, wherein the second feature amount is an absolute value of a first feature amount regarding the second pattern.

4. The method according to claim 1, wherein the second feature amount is a magnitude of a difference between the first feature amount regarding the first pattern and a first feature amount regarding the second pattern.

5. The method according to claim 1, further comprising:

calculating, by the processor, a third feature amount based on layouts of first the and the second patterns; and

comparing, by the processor, the third feature amount with a third threshold, and detecting the critical point in the first pattern.

6. The method according to claim 5, wherein the third feature amount is based on at least one of a distance between the first pattern and the second pattern, a width of the second pattern, and a coverage rate of the second pattern with respect to the first pattern.

7. The method according claim 1, wherein the critical point is detected from the critical point candidate.

8. The method according to claim 1, further comprising selecting at least one of the plurality of algorithms, and displaying, on the display, a detection result of the critical point candidate corresponding to a selected algorithm.

9. The method according to claim 1, further comprising revising the circuit pattern data and/or OPC data in order to eliminate the critical point.

10. The method according to claim 1, wherein when detecting the critical point candidate, in a case where the first feature amount is smaller than the first threshold, detecting the first pattern as the critical point candidate.

11. The method according to claim 1, wherein when detecting the critical point, in a case where the second feature amount is equal to or greater than the second threshold, detecting the first pattern as the critical point.

12. The method according to claim 1, wherein displaying the detection result of the critical point includes simultaneously displaying a display window of the resist image on which the critical point is shown, and a selection window of the plurality of algorithms.

13. The method according to claim 1, wherein displaying the detection result of the critical point includes simultaneously displaying a display window of the resist image on which the critical point is shown, a selection window of the plurality of algorithms, and a setting display window of the second threshold.

14. The method according to claim 1, wherein the second feature amount is based on layouts of the first and the second patterns.

15. The method according to claim 14, wherein the second feature amount is based on at least one of a distance between the first pattern and the second pattern, a width of the second pattern, and a coverage rate of the second pattern with respect to the first pattern.

16. The method according to claim 1, further comprising:

correcting at least one of the circuit pattern data and the OPC condition data; and

transmitting the corrected circuit pattern data and OPC condition data to the external device.