Phase locked loop circuits, clock signal generators comprising digital-to-time convert circuits, operating methods thereof and wireless communication devices

• US 10,606,217 B2
• Filed: 04/03/2019
• Issued: 03/31/2020
• Est. Priority Date: 04/06/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Shin-woong, Kim, Jae-young, Kim, Chul-ho, Jang, Jae-hyuk, Han, Sang-wook
• Primary Examiner(s): Mai, Lam T
• Application Number:
  US16/374,236
• Publication Number:
  US 20190310587A1
• Time in Patent Office: 363 Days
• Field of Search: 341111, 341120, 341152, 327268, 327159, 327292
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/1974 for fractional frequency division
• CPC Class Codes: H04B 17/14 of the whole transmission and reception path, e.g. self-test loop-back
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection

Abstract

Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

Claims

1. A clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator comprising:

a digital-to-time converter (DTC) configured to

delay the reference clock signal based on an input code to generate a delay clock signal, and

output the delay clock signal;

a DTC controller configured to

determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and

generate the input code based on the initial gain value; and

a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

2. The clock signal generator of claim 1, wherein the initial gain value comprises a code value corresponding to a ratio of the period of the previously generated output clock signal to a unit delay amount of the DTC.

3. The clock signal generator of claim 1, wherein the DTC controller comprises a gain calibration circuit configured to:

determine the at least one delay amount of the DTC based on the reference clock signal and at least one previously generated delay clock signal, and

determine the initial gain value by performing a binary search operation based on the result of comparing the at least one delay amount of the DTC with the period of the previously generated output clock signal.

4. The clock signal generator of claim 3, wherein the gain calibration circuit is further configured to complete the binary search operation within a period of time equal to a number of bits of the input code multiplied by a period of the reference clock signal.

5. The clock signal generator of claim 3, wherein the gain calibration circuit comprises:

a first time-to-digital converter configured to convert the at least one delay amount into at least one first digital code;

a second time-to-digital converter configured to convert the period of the previously generated output clock signal into a second digital code;

a comparator configured to compare respective values of the at least one first digital code and the second digital code to generate at least one comparison result; and

a decoder configured to determine the initial gain value based on the at least one comparison result of the comparator.

6. The clock signal generator of claim 3, wherein the gain calibration circuit is activated in response to a frequency lock signal indicating that the previously generated output clock signal has a target frequency.

7. The clock signal generator of claim 1, wherein the phase locked loop comprises:

a phase detector configured to determine a phase difference between the delay clock signal and the division clock signal;

a frequency detector configured to determine a frequency difference between the delay clock signal and the division clock signal;

an oscillator configured to generate the target output clock signal based on the phase difference and the frequency difference;

a divider configured to generate the division clock signal by dividing the previously generated output clock signal; and

a modulator configured to

change an integer division ratio of the divider such that an average division ratio of the divider has a target value, and

provide the DTC with a quantization error value representing a quantization error occurring according to the changed integer division ratio.

8. The clock signal generator of claim 7, wherein the DTC controller comprises a DTC calibration circuit configured to generate control code values based on at least one phase difference between at least one previously generated delay clock signal and the division clock signal, the quantization error value of the phase locked loop, and the initial gain value.

9. The clock signal generator of claim 8, wherein the DTC calibration circuit comprises:

a correlation circuit configured to output correlation values of the at least one phase difference and codes of the quantization error value;

an integrator configured to generate a calibrated gain value by accumulating the correlation values and the initial gain value; and

a multiplier configured to generate the control code values by multiplying the calibrated gain value by the quantization error value.

10. The clock signal generator of claim 9, wherein the DTC controller is further configured to

provide the DTC with the initial gain value as the input code when the previously generated output clock signal has a target frequency, and

provide the DTC with the control code values as the input code when the initial gain value is a target gain value.

11. A phase locked loop circuit comprises:

a phase locked loop configured to generate a target output clock signal based on a division clock signal of a previously generated output clock signal and an input clock signal, the target output clock signal being locked to the input clock signal;

a modulator configured to

change a division ratio of the phase locked loop, and

output an error value occurring according to the changed division ratio;

a digital-to-time converter (DTC) configured to

delay a reference clock signal based on an input code to generate the input clock signal, and

provide the input clock signal to the phase locked loop; and

a DTC controller configured to

determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and

generate the input code based on the initial gain value.

12. The phase locked loop circuit of claim 11, wherein the DTC controller comprises:

a gain calibration circuit configured to determine the initial gain value by performing a binary search operation, based on the result of comparing the at least one delay amount of the DTC with the period of the previously generated output clock signal; and

a DTC calibration circuit configured to output control code values based on at least one phase difference between at least one previously generated first input clock signal and the division clock signal, the error value, and the initial gain value.

13. The phase locked loop circuit of claim 12, wherein the gain calibration circuit comprises:

a comparator configured to compare the at least one delay amount with the period of the previously generated output clock signal to generate a comparison result; and

a decoder configured to perform the binary search operation based on the comparison result received from the comparator.

14. The phase locked loop circuit of claim 12, wherein the gain calibration circuit further comprises:

a logic gate configured to determine the at least one delay amount based on the reference clock signal and at least one previously generated second input clock signal;

a pulse generator configured to generate a pulse signal indicating the period of the previously generated output clock signal; and

a time-to-digital converter configured to convert the at least one delay amount and the pulse signal into digital codes.

15. The phase locked loop circuit of claim 12, wherein the DTC controller further comprises an output control circuit configured to:

select one of the initial gain value or the control code values based on a frequency lock signal output from the phase locked loop and an operation completion signal output from the gain calibration circuit; and

provide the DTC with the selected one of the initial gain value or the control code values as the input code.

16. The phase locked loop circuit of claim 15, wherein the output control circuit is configured to:

select the initial gain value when the frequency lock signal is in an active state and the operation completion signal is in an inactive state; and

select the control code values when the frequency lock signal is in the inactive state or the operation completion signal is in the active state.

17. The phase locked loop circuit of claim 11, wherein the phase locked loop comprises:

a phase detector configured to determine a phase difference between the input clock signal and the division clock signal;

a frequency detector configured to

determine a frequency difference between the input clock signal and the division clock signal, and

generate a frequency lock signal based on the determined frequency difference;

a charge pump configured to generate a current signal corresponding to the phase difference;

a loop filter configured to generate an oscillation control voltage by integrating the current signal;

an oscillator configured to generate the target output clock signal based on the oscillation control voltage; and

a divider configured to generate the division clock signal by dividing the previously generated output clock signal.

18. The phase locked loop circuit of claim 11, wherein the phase locked loop comprises:

a time-to-digital converter configured to

determine a phase difference between the input clock signal and the division clock signal, and

convert the phase difference into a digital value;

a digital loop filter configured to generate an oscillation control signal by integrating the digital value received from the time-to-digital converter;

an oscillator configured to generate the target output clock signal based on the oscillation control signal; and

a divider configured to generate the division clock signal by dividing the previously generated output clock signal.

19. A wireless communication device comprises:

a signal processor configured to

process a transmission signal and a receiving signal in a base band, and

output a frequency control signal;

a transceiver configured to time-serially perform a transmission operation and a receiving operation; and

a clock signal generator configured to generate an target output clock signal used to provide a frequency for sampling the transmission signal and the receiving signal in response to the frequency control signal,

wherein the clock signal generator comprises;

a phase locked loop configured to

generate the target output clock signal based on a division clock signal of a previously generated output clock signal and an input clock signal the target output clock signal being locked to the input clock signal, and

change a division ratio used to generate the division clock signal based on the frequency control signal,

a digital-to-time converter (DTC) configured to

delay a reference clock signal based on an input code to generate the input clock signal, and

provide the input clock signal to the phase locked loop; and

a DTC controller configured to

determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of the previously generated output clock signal, and

generate the input code based on the initial gain value.

20. The wireless communication device of claim 19, wherein the DTC controller comprises:

a gain calibration circuit configured to

compare the at least one delay amount of the DTC with the period of the previously generated output clock signal, and

determine the initial gain value by performing a binary search operation based on the comparison; and

a DTC calibration circuit configured to output control code values based on at least one phase difference between at least one previously generated input clock signal and the division clock signal, an error value according to a change in the division ratio, and the initial gain value.