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Method of reducing power dissipation in a clock distribution network for integrated circuit

  • US 10,606,306 B2
  • Filed: 01/31/2019
  • Issued: 03/31/2020
  • Est. Priority Date: 01/10/2017
  • Status: Active Grant
First Claim
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1. A clock distribution network comprising:

  • a transmission line having a first segment and a second segment;

    a multi-port electrical network coupled between the first segment and second segment of the transmission line, the multi-port electrical network comprising a passive electrical network configured to produce a first resonance and a second resonance that cooperate to create a bandpass response across a plurality of clock distribution frequencies associated with a bandwidth of a combination of the transmission line and the multi-port electrical network; and

    a single input and multiple outputs.

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