Partitioned memory with locally aggregated copy pools

• US 10,606,487 B2
• Filed: 03/17/2017
• Issued: 03/31/2020
• Est. Priority Date: 03/17/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Emma, Philip G., Healy, Michael B., Karkhanis, Tejas, Lin, Ching-Pei
• Primary Examiner(s): Thammavong, Prasith
• Application Number:
  US15/461,568
• Publication Number:
  US 20180267722A1
• Time in Patent Office: 1,110 Days
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1054 the data cache being concurrently physically addressed
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]

Abstract

An aspect includes receiving a request to access data in a memory, the request from a requesting processor and including a virtual address of the data. It is determined, based on contents of a page table that a plurality of physical addresses in the memory corresponds to the virtual address. The physical addresses include a first physical address of a primary memory location in a first partition accessed via a bus that is communicatively coupled to a port of a first processor, and a second physical address of a secondary memory location in a second partition accessed via a bus that is communicatively coupled to a port of a second processor. Contents of the primary memory location in the first partition were previously copied into the secondary memory location. Based on the requesting processor, one of the physical addresses is selected and data at the selected physical address is accessed.

Claims

1. A system comprising:

a memory having computer readable instructions; and

a plurality of processors for executing the computer readable instructions, the computer readable instructions controlling one or more of the plurality of processors to perform operations comprising;

receiving a request to access data in a partitioned memory split across a first and second processor of the plurality of processors, the request from a requesting processor of the plurality of processors and including a virtual address of the data;

determining, based at least in part on contents of a page table, that a plurality of physical addresses in the memory correspond to the virtual address, the physical addresses comprising;

a first physical address of a primary memory location in a first partition accessed via a first memory bus communicatively coupled to a port of the first processor; and

a second physical address of a secondary memory location in a second partition accessed via a second memory bus communicatively coupled to a port of the second processor,

wherein contents of the primary memory location in the first partition were previously copied into the secondary memory location in the second partition;

selecting, based at least in part on the requesting processor, one of the physical addresses; and

accessing the data at the selected physical address.

2. The system of claim 1, wherein the operations further comprise, prior to receiving the request, copying contents of the primary memory location into the secondary memory location and updating the page table to indicate that the virtual address corresponds to both the first physical address and the second physical address, wherein the copying is responsive to the second processor accessing the data more than a threshold number of times, and wherein prior to the copying, the second processor accesses the data at the primary memory location via the first processor and the first memory bus, and subsequent to the copying the second processor accesses the data at the secondary location via the second memory bus.

3. The system of claim 1, wherein the operations further comprise, prior to receiving the request, copying contents of the primary memory location into the secondary memory location and updating the page table to indicate that the virtual address corresponds to both the first physical address and the second physical address, wherein the copying is responsive to a software instruction, and wherein prior to the copying, the second processor accesses the data at the primary memory location via the first processor and the first memory bus, and subsequent to the copying the second processor accesses the data at the secondary location via the second memory bus.

4. The system of claim 1, wherein the access is a write access and the operations further comprises:

invalidating the data stored in the secondary memory location, the invalidating including updating contents of the page table to indicate that a single physical address equal to the first physical address corresponds to the virtual address; and

writing a new data value included in the request to the primary memory location.

5. The system of claim 1, wherein the access is a read access.

6. The system of claim 1, wherein the requesting processor is the second processor and the second physical address is selected.

7. The system of claim 1, wherein the requesting processor is the first processor and the first physical address is selected.

8. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processing device to cause the processing device to perform operations comprising:

receiving a request to access data in a partitioned memory split across a first and second processor of a plurality of processors, the request from a requesting processor of the plurality of processors and including a virtual address of the data;

determining, based at least in part on contents of a page table, that a plurality of physical addresses in the memory correspond to the virtual address, the physical addresses comprising;

a first physical address of a primary memory location in a first partition accessed via a first memory bus communicatively coupled to a port of the first processor; and

a second physical address of a secondary memory location in a second partition accessed via a second memory bus communicatively coupled to a port of the second processor,

wherein contents of the primary memory location in the first partition were previously copied into the secondary memory location in the second partition;

selecting, based at least in part on the requesting processor, one of the physical addresses; and

accessing the data at the selected physical address.

9. The computer program product of claim 8, wherein the program instructions further cause the processor to perform, prior to receiving the request, copying contents of the primary memory location into the secondary memory location and updating the page table to indicate that the virtual address corresponds to both the first physical address and the second physical address, wherein the copying is responsive to the second processor accessing the data more than a threshold number of times, and wherein prior to the copying, the second processor accesses the data at the primary memory location via the first processor and the first memory bus, and subsequent to the copying the second processor accesses the data at the secondary location via the second memory bus.

10. The computer program product of claim 8, wherein the program instructions further cause the processor to perform, prior to receiving the request, copying contents of the primary memory location into the secondary memory location and updating the page table to indicate that the virtual address corresponds to both the first physical address and the second physical address, wherein the copying is responsive to a software instruction, and wherein prior to the copying, the second processor accesses the data at the primary memory location via the first processor and the first memory bus, and subsequent to the copying the second processor accesses the data at the secondary location via the second memory bus.

11. The computer program product of claim 8, wherein the access is a write access and the operations further comprises:

invalidating the data stored in the secondary memory location, the invalidating including updating contents of the page table to indicate that a single physical address equal to the first physical address corresponds to the virtual address; and

writing a new data value included in the request to the primary memory location.