Vector checksum instruction
First Claim
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1. A computer program product for executing an instruction in a central processing unit, the computer program product comprising:
- a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising;
obtaining an instruction for execution, the instruction comprising;
at least one opcode field to provide an opcode, the opcode identifying a Vector Checksum operation;
a first register field to be used to designate a first register, the first register comprising a first operand;
a second register field to be used to designate a second register, the second register comprising a second operand; and
executing the instruction, the executing comprising;
adding together a plurality of elements of the second operand to obtain a first result, wherein the adding comprises performing one or more end around carry add operations;
based on performing an end around carry add operation and producing a sum, adding a carry out of a chosen position of the sum, if any, to a selected position in a selected element of the first operand; and
placing the first result in the selected element of the first operand.
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Abstract
A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.
215 Citations
20 Claims
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1. A computer program product for executing an instruction in a central processing unit, the computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising; obtaining an instruction for execution, the instruction comprising; at least one opcode field to provide an opcode, the opcode identifying a Vector Checksum operation; a first register field to be used to designate a first register, the first register comprising a first operand; a second register field to be used to designate a second register, the second register comprising a second operand; and executing the instruction, the executing comprising; adding together a plurality of elements of the second operand to obtain a first result, wherein the adding comprises performing one or more end around carry add operations; based on performing an end around carry add operation and producing a sum, adding a carry out of a chosen position of the sum, if any, to a selected position in a selected element of the first operand; and placing the first result in the selected element of the first operand. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computer system for executing an instruction in a central processing unit, the computer system comprising:
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a memory; and a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising; obtaining an instruction for execution, the instruction comprising; at least one opcode field to provide an opcode, the opcode identifying a Vector Checksum operation; a first register field to be used to designate a first register, the first register comprising a first operand; a second register field to be used to designate a second register, the second register comprising a second operand; and executing the instruction, the executing comprising; adding together a plurality of elements of the second operand to obtain a first result, wherein the adding comprises performing one or more end around carry add operations; based on performing an end around carry add operation and producing a sum, adding a carry out of a chosen position of the sum, if any, to a selected position in a selected element of the first operand; and placing the first result in the selected element of the first operand. - View Dependent Claims (12, 13, 14, 15)
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16. A computer-implemented method of executing an instruction in a central processing unit, the computer-implemented method comprising:
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obtaining, by a processor, an instruction for execution, the instruction comprising; at least one opcode field to provide an opcode, the opcode identifying a Vector Checksum operation; a first register field to be used to designate a first register, the first register comprising a first operand; a second register field to be used to designate a second register, the second register comprising a second operand; and executing the instruction, the executing comprising; adding together a plurality of elements of the second operand to obtain a first result, wherein the adding comprises performing one or more end around carry add operations; based on performing an end around carry add operation and producing a sum, adding a carry out of a chosen position of the sum, if any, to a selected position in a selected element of the first operand; and placing the first result in the selected element of the first operand. - View Dependent Claims (17, 18, 19, 20)
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Specification