Free form expression accelerator with thread length-based thread assignment to clustered soft processor cores that share a functional circuit

• US 10,606,651 B2
• Filed: 06/20/2015
• Issued: 03/31/2020
• Est. Priority Date: 04/17/2015
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Burger, Douglas C., Heil, Stephen F., Lanka, Sitaram V., Putnam, Andrew R., Smith, Aaron
• Primary Examiner(s): Huisman, David J.
• Application Number:
  US14/745,385
• Publication Number:
  US 20160306772A1
• Time in Patent Office: 1,746 Days
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 2209/5015 Service provider selection
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455

Abstract

A hardware acceleration component is provided that includes a plurality of hardware clusters, each hardware cluster comprising a plurality of soft processor cores and a functional circuit. The plurality of soft processor cores share the functional circuit.

Claims

1. A free form expression executing hardware acceleration component, comprising:

a plurality of hardware processing clusters, each hardware processing cluster comprising;

a first soft processing core comprising a first set of hardware threads;

a second soft processing core comprising a second set of hardware threads independent of the first set of hardware threads;

a functional circuit comprising one or more of a floating point divide circuit, a natural logarithm circuit, an exponent circuit, or a floating point-to-integer circuit; and

a software thread assignment processor that assigns some free form execution software threads to individual ones of the first set of hardware threads based on both a priority assigned to the individual ones of the first set of hardware threads and a length of the free form execution software threads, such that free form execution software threads having the length above a first threshold are assigned to hardware threads having a highest priority, and free form execution software threads having the length below a second threshold are assigned to hardware threads having a lowest priority, the second threshold being less than the first threshold;

wherein the first soft processing core shares the functional circuit with the second soft processing core;

wherein the free form expression executing hardware acceleration component receives feature values, from a remote hardware acceleration component acting as a head component, as input for free form expression processing performed by the free form expression executing hardware acceleration component; and

wherein further the free form expression executing hardware acceleration component is locally communicationally coupled to a first central processing unit that is remote from a second central processing unit, the second central processing unit invoking a service provided by the free form expression executing hardware acceleration component and the remote hardware acceleration component acting as the head component, the second central processing unit being locally communicationally coupled to the remote hardware acceleration component acting as the head component.

2. The free form expression executing hardware acceleration component of claim 1, wherein the first soft processing core further comprises a first pipeline processor that is utilized by individual ones of the first set of hardware threads on a cycle-by-cycle basis and wherein further the second soft processing core further comprises a second pipeline processor that is utilized by individual ones of the second set of hardware threads on a cycle-by-cycle basis.

3. The free form expression executing hardware acceleration component of claim 2, wherein the first soft processing core further comprises a first scheduler that assigns individual priorities to each of the first set of hardware threads and wherein further the second soft processing core further comprises a second scheduler that assigns individual priorities to each of the second set of hardware threads.

4. The free form expression executing hardware acceleration component of claim 1, wherein the software thread assignment processor splits a first free form execution software thread into at least two shorter free form execution software threads and then assigns a first of the at least two shorter free form execution software threads to a first hardware thread of the first set of hardware threads and assigns a second of the at least two shorter free form execution software threads to a second hardware thread of the second set of hardware threads having a same priority as the first hardware thread.

5. The free form expression executing hardware acceleration component of claim 1, wherein the free form expression executing hardware acceleration component is etched on a same die as the first central processing unit.

6. The free form expression executing hardware acceleration component of claim 1, wherein the free form expression executing hardware acceleration component is communicationally coupled to the remote hardware acceleration component acting as the head component independently of either the first central processing unit or the second central processing unit.

7. A method of executing free form expressions on a free form expression executing hardware accelerator, the method comprising:

configuring a plurality of hardware processing clusters on the free form expression executing hardware accelerator to each comprise;

a first soft processing core comprising a first set of hardware threads;

a second soft processing core comprising a second set of hardware threads independent of the first set of hardware threads;

a functional circuit comprising one or more of a floating point divide circuit, a natural logarithm circuit, an exponent circuit, or a floating point-to-integer circuit; and

a software thread assignment processor that assigns some free form execution software threads to individual ones of the first set of hardware threads based on both a priority assigned to the individual ones of the first set of hardware threads and a length of the free form execution software threads, such that free form execution software threads having the length above a first threshold are assigned to hardware threads having a highest priority, and free form execution software threads having the length below a second threshold are is-assigned to hardware threads having a lowest priority, the second threshold being less than the first threshold;

wherein the configuring the plurality of hardware processing clusters comprises configuring the first soft processing core to share the functional circuit with the second soft processing core;

configuring the free form expression executing hardware accelerator to receive feature values, from a remote hardware acceleration component acting as a head component, as input for free form expression processing performed by the free form expression executing hardware accelerator; and

locally communicationally coupling the free form expression executing hardware accelerator to a first central processing unit that is remote from a second central processing unit, the second central processing unit invoking a service provided by the free form expression executing hardware accelerator and the remote hardware acceleration component acting as the head component, the second central processing unit being locally communicationally coupled to the remote hardware acceleration component acting as the head component.

8. The method of claim 7, further comprising configuring the first soft processing core to comprise a first pipeline processor that is utilized by individual ones of the first set of hardware threads on a cycle-by-cycle basis and configuring the second soft processing core to comprise a second pipeline processor that is utilized by individual ones of the second set of hardware threads on a cycle-by-cycle basis.

9. The method of claim 8, further comprising configuring the first soft processing core to comprise a first scheduler that assigns individual priorities to each of the first set of hardware threads and configuring the second soft processing core to comprise a second scheduler that assigns individual priorities to each of the second set of hardware threads.

10. The method of claim 7, further comprising configuring the software thread assignment processor to split a first free form execution software thread into at least two shorter free form execution software threads and then assign a first of the at least two shorter free form execution software threads to a first hardware thread of the first set of hardware threads and assign a second of the at least two shorter free form execution software threads to a second hardware thread of the second set of hardware threads having a same priority as the first hardware thread.

11. The method of claim 7, wherein the free form expression executing hardware accelerator is etched on a same die as the first central processing unit.

12. The method of claim 7, wherein the free form expression executing hardware accelerator is communicationally coupled to the remote hardware acceleration component acting as the head component independently of either the first central processing unit or the second central processing unit.

13. A system comprising:

a first computing device comprising;

a first central processing unit; and

a free form expression executing hardware acceleration component comprising a plurality of hardware processing clusters, each hardware processing cluster comprising;

a first soft processing core comprising a first set of hardware threads;

a second soft processing core comprising a second set of hardware threads independent of the first set of hardware threads;

a functional circuit comprising one or more of a floating point divide circuit, a natural logarithm circuit, an exponent circuit, or a floating point-to-integer circuit; and

a software thread assignment processor that assigns some free form execution software threads to individual ones of the first set of hardware threads based on both a priority assigned to the individual ones of the first set of hardware threads and a length of the free form execution software threads, such that free form execution software threads having the length above a first threshold are assigned to hardware threads having a highest priority, and free form execution software threads having the length below a second threshold are assigned to hardware threads having a lowest priority, the second threshold being less than the first threshold;

wherein the first soft processing core shares the functional circuit with the second soft processing core; and

a second computing device separate from the first computing device, the second computing device comprising;

a second central processing unit; and

a hardware acceleration component acting as a head component;

wherein the hardware acceleration component acting as the head component provides feature values as input for free form expression processing performed by the free form expression executing hardware acceleration component; and

wherein further the second central processing unit invokes a service provided by the free form expression executing hardware acceleration component and the hardware acceleration component acting as the head component.

14. The system of claim 13, wherein the first soft processing core further comprises a first pipeline processor that is utilized by individual ones of the first set of hardware threads on a cycle-by-cycle basis and wherein further the second soft processing core further comprises a second pipeline processor that is utilized by individual ones of the second set of hardware threads on a cycle-by-cycle basis.

15. The system of claim 14, wherein the first soft processing core further comprises a first scheduler that assigns individual priorities to each of the first set of hardware threads and wherein further the second soft processing core further comprises a second scheduler that assigns individual priorities to each of the second set of hardware threads.

16. The system of claim 13, wherein the software thread assignment processor splits a first free form execution software thread into at least two shorter free form execution software threads and then assigns a first of the at least two shorter free form execution software threads to a first hardware thread of the first set of hardware threads and assigns a second of the at least two shorter free form execution software threads to a second hardware thread of the second set of hardware threads having a same priority as the first hardware thread.

17. The system of claim 13, wherein the free form expression executing hardware acceleration component is communicationally coupled to the remote hardware acceleration component acting as the head component independently of either the first central processing unit or the second central processing unit.