Method, system and device for integration of bitcells in a volatile memory array and bitcells in a non-volatile memory array
First Claim
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1. An integrated circuit device, comprising:
- at least a first non-volatile memory array to comprise a first plurality of non-volatile memory bitcells;
at least a first volatile memory array to comprise a first plurality of volatile memory bitcells;
a shared decoder circuit to be coupled to the first non-volatile memory array, and the first volatile memory array to access one or more of the first plurality of non-volatile memory bitcells and one or more of the first plurality of volatile memory bitcells via assertion of one or more access signals;
a shared bus structure to include at least one non-volatile memory bus to transfer memory states from the first plurality of non-volatile bitcells in read operations and to transfer memory states to the first plurality of non-volatile bitcells in write operations, and further to include at least one volatile memory bus to transfer memory states to the first plurality of volatile bitcells in write operations and to transfer memory states from the first plurality of volatile bitcells in read operations; and
at least one external port to transfer signals and/or states representative of input values and/or output values between the shared bus structure and one or more external terminals of the integrated circuit device,wherein the shared bus structure to be coupled to the at least one non-volatile memory bus and the at least one volatile memory bus to enable transfer of signals and/or states between the at least one external port and the at least one non-volatile memory bus or the at least one volatile memory bus, or a combination thereof, and/or to enable a transfer of signals and/or states between the at least one non-volatile memory bus and the at least one volatile memory bus.
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Abstract
Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.
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Citations
24 Claims
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1. An integrated circuit device, comprising:
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at least a first non-volatile memory array to comprise a first plurality of non-volatile memory bitcells; at least a first volatile memory array to comprise a first plurality of volatile memory bitcells; a shared decoder circuit to be coupled to the first non-volatile memory array, and the first volatile memory array to access one or more of the first plurality of non-volatile memory bitcells and one or more of the first plurality of volatile memory bitcells via assertion of one or more access signals; a shared bus structure to include at least one non-volatile memory bus to transfer memory states from the first plurality of non-volatile bitcells in read operations and to transfer memory states to the first plurality of non-volatile bitcells in write operations, and further to include at least one volatile memory bus to transfer memory states to the first plurality of volatile bitcells in write operations and to transfer memory states from the first plurality of volatile bitcells in read operations; and at least one external port to transfer signals and/or states representative of input values and/or output values between the shared bus structure and one or more external terminals of the integrated circuit device, wherein the shared bus structure to be coupled to the at least one non-volatile memory bus and the at least one volatile memory bus to enable transfer of signals and/or states between the at least one external port and the at least one non-volatile memory bus or the at least one volatile memory bus, or a combination thereof, and/or to enable a transfer of signals and/or states between the at least one non-volatile memory bus and the at least one volatile memory bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method comprising:
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applying, via a shared decoder circuit, a first access signal to at least a first wordline of a plurality of wordlines to access one or more volatile memory bitcells in a first volatile memory array formed in an integrated circuit device and one or more non-volatile memory bitcells in a non-volatile memory array formed in the integrated circuit device; applying one or more first signals to one or more external terminals of the integrated circuit device to access at least some volatile memory bitcells in the first volatile memory array; and applying one or more second signals to the one or more external terminals of the integrated circuit device to access at least some of the one or more non-volatile memory bitcells in the non-volatile memory array, wherein the one or more external terminals are coupled to a port of the integrated circuit device for accessing the first volatile memory array or the non-volatile memory array, or a combination thereof. - View Dependent Claims (18, 19, 20)
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21. A method comprising:
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applying one or more first signals to one or more external terminals of an integrated circuit device to access one or more volatile memory bitcells in a volatile memory array formed in an integrated circuit device; and applying one or more second signals to the one or more external terminals of the integrated circuit device to access one or more non-volatile memory bitcells in a non-volatile memory array formed in the integrated circuit device, wherein at least one of the one or more volatile memory bitcells and at least one of the one or more non-volatile memory bitcells are connected to a wordline of a plurality of wordlines formed in the integrated circuit device, wherein a shared decoder circuit coupled to the first non-volatile memory array and the first volatile memory array to access the one or more non-volatile memory bitcells and the one or more volatile memory bitcells by applying an access signal to the wordline of the plurality of wordlines, and wherein the one or more external terminals are coupled to a port of the integrated circuit device, the port for accessing the volatile memory array or the non-volatile memory array, or a combination thereof. - View Dependent Claims (22, 23, 24)
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Specification