Sensing a memory cell
First Claim
1. A device, comprising:
- a memory cell configured to store a logic state;
a capacitor configured to integrate a charge associated with the memory cell during a read operation;
a sense component configured to determine the logic state stored on the memory cell during the read operation;
a first cascode coupled with the memory cell and a first node;
a second cascode coupled with the capacitor and the first node, wherein the second cascode is configured to isolate the first node from the capacitor based at least in part on a voltage of a digit line failing to satisfy a threshold; and
a transistor coupled with the first node and the sense component and configured to selectively couple the first node with the sense component during the read operation after the capacitor is isolated from the first node.
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Accused Products
Abstract
Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a cascode may couple a precharged capacitor with the memory cell to transfer a charge between the precharged capacitor and the memory cell. The cascode may isolate the capacitor from the memory cell based on the charge transferred between the capacitor and the memory cell. A second capacitor (e.g., a parasitic capacitor) may continue to provide an additional amount of charge to the memory cell during the read operation. Such a change in capacitance value during the read operation may provide a large sense window due to a non-linear voltage characteristics associated with the change in capacitance value.
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Citations
23 Claims
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1. A device, comprising:
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a memory cell configured to store a logic state; a capacitor configured to integrate a charge associated with the memory cell during a read operation; a sense component configured to determine the logic state stored on the memory cell during the read operation; a first cascode coupled with the memory cell and a first node; a second cascode coupled with the capacitor and the first node, wherein the second cascode is configured to isolate the first node from the capacitor based at least in part on a voltage of a digit line failing to satisfy a threshold; and a transistor coupled with the first node and the sense component and configured to selectively couple the first node with the sense component during the read operation after the capacitor is isolated from the first node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method, comprising:
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precharging a digit line to a first voltage; precharging a capacitor to a second voltage, the capacitor being configured to integrate a charge associated with a memory cell during a read operation; transferring the charge between the memory cell and the capacitor through a first cascode and a second cascode during the read operation, the first cascode being coupled with the memory cell and a first node associated with a sense component, and the second cascode being coupled with the capacitor and the first node; isolating the first node from the capacitor based at least in part on transferring the charge and on a voltage of the digit line failing to satisfy a threshold; coupling, using a transistor, the first node with the sense component after isolating the first node from the capacitor; and determining a logic state stored on the memory cell based at least in part on coupling the first node with the sense component. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A memory device, comprising:
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a memory array comprising a memory cell coupled with a digit line; a controller coupled with the memory array and with a capacitor configured to integrate a charge associated with the memory cell during a read operation, the controller configured to cause the memory device; precharge the digit line to a first voltage; precharge the capacitor to a second voltage; transfer the charge between the memory cell and the capacitor through a first cascode and a second cascode during the read operation, the first cascode being coupled with the memory cell and a first node associated with a sense component, and the second cascode being coupled with the capacitor and the first node; isolate the first node from the capacitor based at least in part on transferring the charge and on a voltage of the digit line failing to satisfy a threshold; couple, using a transistor, the first node with the sense component after isolating the first node from the capacitor; and determine a logic state stored on the memory cell based at least in part on coupling the first node with the sense component.
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Specification