Gate aligned contact and method to fabricate same

• US 10,607,884 B2
• Filed: 05/14/2019
• Issued: 03/31/2020
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Golonzka, Oleg, Sivakumar, Swaminathan, Wallace, Charles H., Ghani, Tahir
• Primary Examiner(s): Henry, Caleb E
• Application Number:
  US16/412,210
• Publication Number:
  US 20190267286A1
• Time in Patent Office: 322 Days
• Field of Search: 257382
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

Claims

1. An integrated circuit structure, comprising:

a fin comprising silicon, the fin having a length along a first direction;

a first gate structure over the fin and along a second direction orthogonal to the first direction, the first gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers;

a second gate structure over the fin and along the second direction, the second gate structure adjacent the first gate structure, and the second gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers;

a third gate structure over the fin and along the second direction, the third gate structure adjacent the second gate structure, and the third gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers;

a fourth gate structure over the fin and along the second direction, the fourth gate structure adjacent the third gate structure, and the fourth gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers;

a first conductive contact structure over the fin and along the second direction, the first conductive contact structure between the first gate structure and the second gate structure, and the first conductive contact structure having a top surface substantially co-planar with a top surface of the dielectric cap of the first gate structure and with the dielectric cap of the second gate structure;

a second conductive contact structure over the fin and along the second direction, the second conductive contact structure between the second gate structure and the third gate structure, and the second conductive contact structure having a top surface substantially co-planar with a top surface of the dielectric cap of the second gate structure and with the dielectric cap of the third gate structure; and

a third conductive contact structure over the fin and along the second direction, the third conductive contact structure between the third gate structure and the fourth gate structure, and the third conductive contact structure having a top surface substantially co-planar with a top surface of the dielectric cap of the third gate structure and with the dielectric cap of the fourth gate structure.

2. The integrated circuit structure of claim 1, wherein the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure have substantially a same length along the second direction.

3. The integrated circuit structure of claim 2, wherein the first conductive contact structure, the second conductive contact structure, and the third conductive contact structure have substantially a same length along the second direction.

4. The integrated circuit structure of claim 1, wherein the first conductive contact structure, the second conductive contact structure, and the third conductive contact structure have substantially a same length along the second direction.

5. The integrated circuit structure of claim 1, wherein the dielectric cap of each of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure comprises silicon carbide.

6. The integrated circuit structure of claim 1, wherein the dielectric cap of each of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure comprises a dielectric material different than a dielectric material of the sidewall spacers of each of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure.

7. The integrated circuit structure of claim 1, wherein the gate dielectric layer of each of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure comprises a high-K gate dielectric layer.

8. An integrated circuit structure, comprising:

a fin comprising silicon, the fin having a length along a first direction;

a second fin comprising silicon, the second fin having a length along the first direction, and the second fin separated from the fin by an isolation structure;

a first conductive contact structure over the fin and along a second direction orthogonal to the first direction;

a second conductive contact structure over the fin and along the second direction, the second conductive contact structure adjacent the first conductive contact structure;

a third conductive contact structure over the fin and along the second direction, the third conductive contact structure adjacent the second conductive contact structure, wherein the first conductive contact structure, the second conductive contact structure, and the third conductive contact structure have substantially a same length along the second direction, and wherein one or more of the first conductive contact structure, the second conductive contact structure, or the third conductive contact structure extends over the isolation structure and over the second fin;

a first gate structure over the fin and along the second direction, the first gate structure between the first conductive contact structure and the second conductive contact structure, the first gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers, wherein the dielectric cap of the first gate structure has a top surface substantially co-planar with a top surface of the first conductive contact structure and with a top surface of the second conductive contact structure; and

a second gate structure over the fin and along the second direction, the second gate structure between the second conductive contact structure and the third conductive contact structure, the second gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers, wherein the dielectric cap of the second gate structure has a top surface substantially co-planar with a top surface of the second conductive contact structure and with a top surface of the third conductive contact structure, and wherein the first gate structure and the second gate structure have substantially a same length along the second direction.

9. The integrated circuit structure of claim 8, wherein the dielectric cap of each of the first gate structure and the second gate structure comprises silicon carbide.

10. The integrated circuit structure of claim 8, wherein the dielectric cap of each of the first gate structure and the second gate structure comprises a dielectric material different than a dielectric material of the sidewall spacers of each of the first gate structure and the second gate structure.

11. The integrated circuit structure of claim 8, wherein the gate dielectric layer of each of the first gate structure and the second gate structure comprises a high-K gate dielectric layer.

12. A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising;

a fin comprising silicon, the fin having a length along a first direction;

a first gate structure over the fin and along a second direction orthogonal to the first direction, the first gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers;

a second gate structure over the fin and along the second direction, the second gate structure adjacent the first gate structure, and the second gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers;

a third gate structure over the fin and along the second direction, the third gate structure adjacent the second gate structure, and the third gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers;

a fourth gate structure over the fin and along the second direction, the fourth gate structure adjacent the third gate structure, and the fourth gate structure comprising a gate dielectric layer, a metal gate, sidewall spacers, and a dielectric cap laterally adjacent to the sidewall spacers;

a first conductive contact structure over the fin and along the second direction, the first conductive contact structure between the first gate structure and the second gate structure, and the first conductive contact structure having a top surface substantially co-planar with a top surface of the dielectric cap of the first gate structure and with the dielectric cap of the second gate structure;

a second conductive contact structure over the fin and along the second direction, the second conductive contact structure between the second gate structure and the third gate structure, and the second conductive contact structure having a top surface substantially co-planar with a top surface of the dielectric cap of the second gate structure and with the dielectric cap of the third gate structure; and

a third conductive contact structure over the fin and along the second direction, the third conductive contact structure between the third gate structure and the fourth gate structure, and the third conductive contact structure having a top surface substantially co-planar with a top surface of the dielectric cap of the third gate structure and with the dielectric cap of the fourth gate structure.

13. The computing device of claim 12, further comprising:

a memory coupled to the board.

14. The computing device of claim 12, further comprising:

a communication chip coupled to the board.

15. The computing device of claim 12, further comprising:

a camera coupled to the board.

16. The computing device of claim 12, further comprising:

a battery coupled to the board.

17. The computing device of claim 12, further comprising:

an antenna coupled to the board.

18. The computing device of claim 12, wherein the component is a packaged integrated circuit die.

19. The computing device of claim 12, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

20. The computing device of claim 12, wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.