Method for forming a semiconductor device structure comprising a gate fill metal
First Claim
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1. A method for forming a semiconductor device structure comprising:
- depositing an NMOS gate dielectric over a semiconductor substrate in a NMOS gate trench and depositing a PMOS gate dielectric over the semiconductor substrate in a PMOS gate trench;
depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric;
depositing a liner layer directly onto the first work function metal;
removing the first work function metal and the liner layer over the PMOS gate dielectric; and
depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, wherein the second work function metal is deposited directly onto the liner layer in the NMOS gate trench such that the second work function metal spans a surface of the liner layer within the NMOS gate trench,wherein depositing the second work function metal comprises filling a remainder of the PMOS gate trench and a remainder of the NMOS gate trench with the second work function metal.
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Abstract
A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.
2556 Citations
65 Claims
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1. A method for forming a semiconductor device structure comprising:
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depositing an NMOS gate dielectric over a semiconductor substrate in a NMOS gate trench and depositing a PMOS gate dielectric over the semiconductor substrate in a PMOS gate trench; depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric; depositing a liner layer directly onto the first work function metal; removing the first work function metal and the liner layer over the PMOS gate dielectric; and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, wherein the second work function metal is deposited directly onto the liner layer in the NMOS gate trench such that the second work function metal spans a surface of the liner layer within the NMOS gate trench, wherein depositing the second work function metal comprises filling a remainder of the PMOS gate trench and a remainder of the NMOS gate trench with the second work function metal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A method for forming a semiconductor device structure comprising:
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depositing an NMOS gate dielectric over a semiconductor substrate in a NMOS gate trench and depositing a PMOS gate dielectric over the semiconductor substrate in a PMOS gate trench; depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric; depositing a liner layer directly onto the first work function metal; removing the first work function metal and the liner layer over the PMOS gate dielectric; and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, wherein the second work function metal is deposited directly onto the liner layer in the NMOS gate trench such that the second work function metal spans a surface of the liner layer within the NMOS gate trench, wherein the second work function metal comprises a molybdenum film comprising a gate fill metal. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65)
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Specification
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Current AssigneeASM IP Holding B.V. (ASM International NV)
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Original AssigneeASM IP Holdings B.V.
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InventorsXie, Qi, Zhu, Chiyu, Shrestha, Kiran, Calka, Pauline, Madia, Oreste, Maes, Jan Willem, Givens, Michael Eugene
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Primary Examiner(s)Garces, Nelson
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Application NumberUS15/707,786Publication NumberTime in Patent Office925 DaysField of SearchUS Class CurrentCPC Class CodesH01L 21/823842 gate conductors with differ...H01L 27/092 complementary MIS field-eff...H01L 29/495 the conductor material next...H01L 29/4966 the conductor material next...H01L 29/513 the variation being perpend...H01L 29/517 the insulating material com...
