Semiconductor devices for integration with light emitting chips and modules thereof

• US 10,607,972 B2
• Filed: 05/08/2018
• Issued: 03/31/2020
• Est. Priority Date: 11/18/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Bonart, Dietrich, Weidgans, Bernhard, Gatterbauer, Johann, Gross, Thomas, Heigl, Martina
• Primary Examiner(s): Ngo, Ngan V
• Application Number:
  US15/974,299
• Publication Number:
  US 20180308830A1
• Time in Patent Office: 693 Days
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2933/0058 relating to optical field-shaping elements
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 31/055 where light is absorbed and re-emitted at a different wavelength by the optical element directly associated or integrated with the PV cell, e.g. by using luminescent material, fluorescent concentrators or up-conversion arrangements
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/405 : Reflective materials
• CPC Class Codes: H01L 33/44 : characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/46 : Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/60 : Reflective elements
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H10K 50/856 : comprising reflective means
• CPC Class Codes: Y02E 10/52 : PV systems with concentrators

Abstract

A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate comprising a main surface and one or more active components formed in the substrate;

an interconnect portion formed on the main surface and comprising an upper surface opposite the main surface;

two contact pads disposed at the upper surface;

an opening between the two contact pads that exposes dielectric material of the interconnect portion at the upper surface;

a reflective structure disposed within the interconnect portion beneath the opening,

wherein the reflective structure is electrically isolated from all of the active components formed in the substrate.

2. The semiconductor device of claim 1, wherein from a plan view perspective of the semiconductor device, the reflective structure completely overlaps with the opening.

3. The semiconductor device of claim 2, wherein an area of the reflective structure is at least ten percent greater than an area of the opening.

4. The semiconductor device of claim 1, further comprising a light emitting diode (LED) chip directly soldered to one of the contact pads.

5. A semiconductor device, comprising:

a semiconductor substrate comprising a main surface;

an interconnect portion formed on the main surface and comprising an upper surface opposite the main surface;

two contact pads disposed at the upper surface;

an opening between the two contact pads that exposes dielectric material of the interconnect portion at the upper surface;

a reflective structure disposed within the interconnect portion beneath the opening;

wherein from a plan view perspective of the semiconductor device, the reflective structure completely overlaps with the opening, and

wherein the contact pads and the reflective structure collectively form part of a multi-level light reflective layer that occupies an entire area of the upper surface of the interconnect portion.

6. The semiconductor device of claim 5, wherein the multi-level light reflective layer comprises a plurality of the light reflective structures.

7. The semiconductor device of claim 5, wherein the multi-level light reflective layer is configured to reflect all light in visible wavelength above 400 nm that is externally directed towards the upper surface of the interconnect portion.

8. A semiconductor device, comprising:

a semiconductor substrate comprising a main surface;

an interconnect portion formed on the main surface and comprising an upper surface opposite the main surface;

two contact pads disposed at the upper surface;

an opening between the two contact pads that exposes dielectric material of the interconnect portion at the upper surface;

a reflective structure disposed within the interconnect portion beneath the opening,

wherein the interconnect portion comprises a first metallization layer formed on the main surface of the substrate, wherein the first metallization layer comprises two metal line sections that are spaced apart from one another by a gap, and wherein the reflective structure is disposed over the gap.

9. The semiconductor device of claim 8, wherein the interconnect portion further comprises a dielectric region formed on the main surface within the gap, wherein the dielectric region is transparent or translucent, and wherein the reflective structure completely covers the dielectric region.

10. The semiconductor device of claim 8, wherein the interconnect portion further comprises a passivation layer disposed over the first metallization layer and a second metal portion formed on the passivation layer, wherein the reflective structure is formed on the second metal portion.

11. The semiconductor device of claim 10, wherein the second metal portion comprises a refractory metal, and wherein the reflective structure comprises a reflective metal.

12. The semiconductor device of claim 10, further comprising a protective layer conformally deposited on the passivation layer and a stack that includes the second metal portion and the reflective structure.

13. The semiconductor device of claim 8, wherein a material composition of the reflective structure is different from a material composition of the contact pads and a material composition of the first metallization layer.

14. The semiconductor device of claim 8, wherein the reflective structure is electrically disconnected from the first metallization layer and from each of the contact pads.