Offset interposers for large-bottom packages and large-die package-on-package structures

• US 10,607,976 B2
• Filed: 03/31/2016
• Issued: 03/31/2020
• Est. Priority Date: 08/16/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mortensen, Russell K., Nickerson, Robert M., Watts, Nicholas R.
• Primary Examiner(s): Chen, Xiaoliang
• Application Number:
  US15/087,153
• Publication Number:
  US 20160218093A1
• Time in Patent Office: 1,461 Days
• Field of Search: 174261, 257686, 257737, 257738, 257767, 438106, 438108, 438109, 438122, 438460
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/08238 the bonding area connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 : Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/43 : Manufacturing methods
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/143 : Digital devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1511 : Structure
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 3/4038 : Through-connections; Vertical interconnect access [VIA] connections H05K3/403, H05K3/42 take precedence
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.

Abstract

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Claims

1. A package-on-package (POP) structure comprising:

a processor device mechanically and electrically coupled to a first substrate;

a first ball grid array (BGA) electrically and mechanically coupled to the processor;

an interposer electrically and mechanically coupled to the first substrate, wherein the interposer comprises;

a first side comprising a first array of pads, wherein a first pad and a second pad of the first array are adjacent to each other on the first side and the first pad of the first array is spaced from the second pad of the first array at a first pitch, and wherein the first pad of the first array is coupled to a first electrical interconnect structure of the first BGA, and wherein the second pad of the first array is coupled to a second electrical interconnect structure of the first BGA, and wherein the first array of pads comprises a first perimeter dimension; and

a second side comprising a second array of pads, wherein a first pad and a second pad of the second array are adjacent to each other on the second side and the first pad of the second array is spaced from the second pad of the second array at a second pitch, and the second pitch is different than the first pitch, and wherein the first pad on the second side is electrically coupled with the first pad on the first side through the interposer, and wherein the second pad on the second side and the second pad on the first side are electrically coupled to each other through the interposer, and wherein the second array of pads comprises a second perimeter dimension, wherein the first perimeter dimension is larger than the second perimeter dimension;

a second BGA comprising a plurality of electrical interconnect structures, wherein the first pad of the second array of pads is coupled with a first electrical interconnect structure of the second BGA, and wherein the second pad of the second array of pads is coupled with a second electrical interconnect structure of the second BGA; and

a memory device mechanically and electrically coupled to a second substrate, and the second substrate is mechanically and electrically coupled to the second BGA, wherein the memory device includes a die, and the first electrical interconnect structure of the second BGA is located within a footprint of the die, and the second electrical interconnect structure of the second BGA is located outside the footprint of the die.

2. The structure of claim 1 wherein the first pad array comprises a land side pad array, and wherein the second pad array comprises a package on package (POP) side pad array, and wherein a first pad of the land side array is electrically coupled to a first POP side pad by direct contact with a via interconnect structure.

3. The structure of claim 1 wherein a center to center spacing between the first pad and the second pad of the first pad array does not overlap the center to center spacing between the first pad and the second pad of the second pad array.

4. The structure of claim 1 wherein a center to center spacing between the first pad and the second pad of the first array overlaps a center to center spacing between the pad and the second pad of the second pad array.

5. The structure of claim 1 wherein the first and second electrical interconnects of the first BGA comprise electrical bumps, and wherein the first and second electrical connects of the second BGA comprise electrical bumps.

6. The structure of claim 1 wherein the memory device is mechanically and electrically coupled to the second side of interposer through the second BGA.

7. The structure of claim 1, wherein the processor comprises a portion of a first package, and wherein the memory device comprises a portion of a second package.

8. The structure of claim 1 wherein the memory device is electrically coupled to the second substrate by one of a wire bond connection or a flip chip connection.

9. The structure of claim 1, wherein the second substrate has a smaller area than the first substrate.

10. The structure of claim 1, wherein the second pitch is greater than the first pitch.

11. The structure of claim 1, wherein:

the second substrate includes a first memory interconnect and a second memory interconnect;

the first memory interconnect is located within the footprint of the die, and the first electrical interconnect structure is coupled with the first memory interconnect; and

the second memory interconnect is located outside the footprint of the die, and the second electrical interconnect structure is coupled with the second memory interconnect.